Triple 3-input NAND gate

74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

8-Bit Schottky Barrier Diode Array

General Description The 74F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress negative transients caused by line reflections, switching noise and crosstalk. Features ■ 8-Bit a

8-Bit Schottky Barrier Diode Array

General Description The 74F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress negative transients caused by line reflections, switching noise and crosstalk. Features ■ 8-Bit a

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Positive J-K positive edge-triggered flip-flops

DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

Triple 3-input NAND gate

74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

Dual J-K negative edge-triggered flip-flop

DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo

Dual J-K negative edge-triggered flip-flops without reset

DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inp

Dual J-K negative edge-triggered flip-flop with common clock and reset

DESCRIPTION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inp

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inp

Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

Octal inverter buffer 3-State

DESCRIPTION The 74F1240 and 74F1241 are octal buffers that are ideal for driving bus lines or buffer memory address registers. The outputs are capable of sinking 64mA and sourcing up to 15mA, producing very good capacitive drive characteristics. The device features two Output Enables, OEa and OEb

Octal inverter buffer 3-State

DESCRIPTION The 74F1240 and 74F1241 are octal buffers that are ideal for driving bus lines or buffer memory address registers. The outputs are capable of sinking 64mA and sourcing up to 15mA, producing very good capacitive drive characteristics. The device features two Output Enables, OEa and OEb

Octal buffer 3-State

DESCRIPTION The 74F1244 is an octal buffer that is ideal for driving bus lines or buffer memory address registers. FEATURES • High impedance NPN base inputs for reduced loading (20µA in High and Low states) • Low power, light loading • Functional pin-for-pin equivalent of 74F244 • 1/30t

Octal transceiver 3-State

DESCRIPTION The 74F1245 is an octal transceiver featuring non-inverting 3-State bus compatible outputs in both transmit and receive directions. The B port outputs are capable of sinking 64mA and sourcing up to 15mA, producing very good capacitive drive characteristics. The device features an Outp

Quad buffers 3-State

FEATURE • High impedance NPN base inputs for reduced loading (20µA in High and Low states)

Quad Buffer (3-STATE)

Features ■ High impedance base inputs for reduced loading

Quad Buffer (3-STATE)

Features ■ High impedance base inputs for reduced loading

Quad Buffer (3-STATE)

Features ■ High impedance base inputs for reduced loading

Quad Buffer (3-STATE)

Features ■ High impedance base inputs for reduced loading

Quad Buffer (3-STATE)

Features ■ High impedance base inputs for reduced loading

Quad Buffer (3-STATE)

Features ■ High impedance base inputs for reduced loading

Quad Buffer (3-STATE)

Features ■ High impedance base inputs for reduced loading

Quad Buffer (3-STATE)

Features ■ High impedance base inputs for reduced loading

Quad buffers 3-State

FEATURE • High impedance NPN base inputs for reduced loading (20µA in High and Low states)

Quad 2-input NAND Schmitt trigger

DESCRIPTION The 74F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have greater noise margin th

Quad 2-Input NAND Schmitt Trigger

General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise m

Quad 2-input NAND Schmitt trigger

DESCRIPTION The 74F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have greater noise margin

Quad 2-Input NAND Schmitt Trigger

General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise m

Quad 2-Input NAND Schmitt Trigger

General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise m

Quad 2-Input NAND Schmitt Trigger

General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise m

13.input NAND Gate

13-input NAND gate

13-input NAND gate

FEATURE • Industrial temperature range available (–40°C to +85°C) TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F133 4.0ns 2.0mA