位置：首页 > IC中文资料第9367页 > 74F109
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74F109 | Positive J-K positive edge-triggered flip-flops DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are | PHILIPS 飞利浦 |   | |
74F109 | Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J | FAIRCHILD 仙童半导体 | | |
74F109 | Positive J-K positive edge-triggered flip-flops | ETC 知名厂家 | ETC | |
74F109 | Dual JK Positive Edge-Triggered Flip-Flop | ONSEMI 安森美半导体 | | |
74F109 | Dual JK Positive Edge-Triggered Flip-Flop 文件：80.64 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | |
Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J | FAIRCHILD 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J | FAIRCHILD 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop General Description\nThe ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K ■ Guaranteed 4000V minimum ESD protection.; | TI 德州仪器 | | ||
Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J | FAIRCHILD 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：80.64 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：80.64 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：133.12 Kbytes Page：10 Pages | NSC 国半 | | ||
Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop 文件：384.64 Kbytes Page：12 Pages | TI 德州仪器 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：133.12 Kbytes Page：10 Pages | NSC 国半 | | ||
Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop 文件：384.64 Kbytes Page：12 Pages | TI 德州仪器 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：80.64 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：80.64 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | ||
Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop 文件：384.64 Kbytes Page：12 Pages | TI 德州仪器 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：133.12 Kbytes Page：10 Pages | NSC 国半 | | ||
Positive J-K positive edge-triggered flip-flops DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are | PHILIPS 飞利浦 | | ||
Positive J-K positive edge-triggered flip-flops DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are | PHILIPS 飞利浦 | |
74F109产品属性
- 类型
描述
- 型号
74F109
- 制造商
FAIRCHILD
- 制造商全称
Fairchild Semiconductor
- 功能描述
Dual JK Positive Edge-Triggered Flip-Flop
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
FAIRCHIL |
25+ |
SOP-16 |
4500 |
全新原装、诚信经营、公司现货销售 |
|||
FAIRCHILD |
1999 |
SOP-16 |
920 |
原装现货海量库存欢迎咨询 |
|||
Fairchild Semiconductor |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
TOS |
SOP |
270 |
正品原装--自家现货-实单可谈 |
||||
Sig |
25+ |
28 |
公司优势库存 热卖中!! |
||||
ph |
24+ |
N/A |
6980 |
原装现货,可开13%税票 |
|||
FAIRCHILD/仙童 |
2223+ |
SOIC-16 |
26800 |
只做原装正品假一赔十为客户做到零风险 |
|||
NS |
24+ |
LCC |
1025 |
原装优势现货 |
|||
F |
22+ |
CDIP |
12245 |
现货,原厂原装假一罚十! |
|||
NSC |
2450+ |
DIP |
8850 |
只做原装正品假一赔十为客户做到零风险!! |
74F109规格书下载地址
74F109参数引脚图相关
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- 74F00SJ
74F109数据表相关新闻
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2024-7-1174F08M，74F1016DW，74F109D，74F109DR，74F109N，74F10D，
74F08M，74F1016DW，74F109D，74F109DR，74F109N，74F10D，
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74FCT245ATSOC
2019-3-4
DdatasheetPDF页码索引
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