Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

Triple 3-input NAND gate

74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate

Triple 3-Input NAND Gate

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Triple 3-Input NAND Gate

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Triple 3-input AND gate

Triple 3-Input NAND Gate

8-Bit Schottky Barrier Diode Array

General Description The 74F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress negative transients caused by line reflections, switching noise and crosstalk. Features ■ 8-Bit a

8-Bit Schottky Barrier Diode Array

General Description The 74F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress negative transients caused by line reflections, switching noise and crosstalk. Features ■ 8-Bit a

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Positive J-K positive edge-triggered flip-flops

DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

Triple 3-Input NAND Gate

文件：64.5 Kbytes Page：5 Pages

High Q, high self-resonant frequency Varnish coated

文件：429.04 Kbytes Page：1 Pages

色环/插件电感

封装/外壳：轴向 包装：散装 描述：FIXED IND 100UH 100MA 6 OHM TH 电感器，线圈，扼流圈 固定电感器

封装/外壳：轴向 包装：散装 描述：FIXED IND 10UH 250MA 3 OHM TH 电感器，线圈，扼流圈 固定电感器

High Q, high self-resonant frequency Varnish coated

文件：429.04 Kbytes Page：1 Pages

High Q, high self-resonant frequency Varnish coated

文件：429.04 Kbytes Page：1 Pages

18-Bit Undershoot/Overshoot Clamp and ESD Protection Device

文件：99.89 Kbytes Page：6 Pages

18-Bit Undershoot/Overshoot Clamp and ESD Protection Device

文件：99.89 Kbytes Page：6 Pages

18-Bit Undershoot/Overshoot Clamp and ESD Protection Device

文件：99.89 Kbytes Page：6 Pages

18-Bit Undershoot/Overshoot Clamp and ESD Protection Device

文件：99.89 Kbytes Page：6 Pages

18-Bit Undershoot/Overshoot Clamp and ESD Protection Device

文件：99.89 Kbytes Page：6 Pages

18-Bit Undershoot/Overshoot Clamp and ESD Protection Device

文件：99.89 Kbytes Page：6 Pages

18-Bit Undershoot/Overshoot Clamp and ESD Protection Device

文件：99.89 Kbytes Page：6 Pages

18-Bit Undershoot/Overshoot Clamp and ESD Protection Device

文件：99.89 Kbytes Page：6 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：80.64 Kbytes Page：7 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：80.64 Kbytes Page：7 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：80.64 Kbytes Page：7 Pages

Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop

文件：384.64 Kbytes Page：12 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：133.12 Kbytes Page：10 Pages

Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop

文件：384.64 Kbytes Page：12 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：133.12 Kbytes Page：10 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：80.64 Kbytes Page：7 Pages

Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop

文件：384.64 Kbytes Page：12 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：80.64 Kbytes Page：7 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：133.12 Kbytes Page：10 Pages

Triple 3-Input NAND Gate

文件：140.66 Kbytes Page：6 Pages

Triple 3-Input NAND Gate

文件：64.5 Kbytes Page：5 Pages

Triple 3-Input NAND Gate

文件：64.5 Kbytes Page：5 Pages

Triple 3-Input NAND Gate

文件：140.66 Kbytes Page：6 Pages

Triple 3-Input NAND Gate

文件：140.66 Kbytes Page：6 Pages

Triple 3-Input NAND Gate

文件：64.5 Kbytes Page：5 Pages