型号 功能描述 生产厂家 企业 LOGO 操作
74F114

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inp

Fairchild

仙童半导体

74F114

Dual J-K negative edge-triggered flip-flop with common clock and reset

DESCRIPTION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table

Philips

飞利浦

74F114

Dual J-K negative edge-triggered flip-flop with common clock and reset

ETC

知名厂家

74F114

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

ONSEMI

安森美半导体

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inp

Fairchild

仙童半导体

Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig gering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inp

Fairchild

仙童半导体

封装/外壳:14-DIP(0.300",7.62mm) 功能:设置(预设)和复位 包装:袋 描述:IC FF JK TYPE DUAL 1BIT 14DIP 集成电路(IC) 触发器

ONSEMI

安森美半导体

Dual J-K negative edge-triggered flip-flop with common clock and reset

DESCRIPTION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table

Philips

飞利浦

74F114产品属性

  • 类型

    描述

  • 型号

    74F114

  • 制造商

    Fairchild Semiconductor Corporation

更新时间:2025-12-25 23:01:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
onsemi(安森美)
24+
SOP14
2669
只做原装,提供一站式配单服务,代工代料。BOM配单
S
24+
NA/
3995
原装现货,当天可交货,原型号开票
FSC
2016+
DIP
3000
只做原装,假一罚十,公司可开17%增值税发票!
NSC
23+
NA
20000
全新原装假一赔十
FAIR
23+
NA
9856
原装正品,假一罚百!
恩XP
23+
DIP14
13852
原厂授权代理,海外优势订货渠道。可提供大量库存,详
FAIRCHILD
25+
DIP
4500
全新原装、诚信经营、公司现货销售
24+
DIP
100
fsc
24+
N/A
6980
原装现货,可开13%税票
FAIRCHILD
50
全新原装 货期两周

74F114数据表相关新闻