型号 功能描述 生产厂家&企业 LOGO 操作
74F109SC

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

74F109SC

Dual JK Positive Edge-Triggered Flip-Flop

文件:80.64 Kbytes Page:7 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

74F109SC

Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop

文件:384.64 Kbytes Page:12 Pages

TI1

德州仪器

74F109SC

封装/外壳:16-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:管件 描述:IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路(IC) 触发器

ONSEMI

安森美半导体

74F109SC

Dual JK Positive Edge-Triggered Flip-Flop

文件:133.12 Kbytes Page:10 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Positive J-K positive edge-triggered flip-flops

DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are

Philips

飞利浦

Dual JK Positive Edge-Triggered Flip-Flop

文件:80.64 Kbytes Page:7 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

封装/外壳:16-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:管件 描述:IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路(IC) 触发器

ONSEMI

安森美半导体

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual JK Positive Edge-Triggered Flip-Flop

文件:133.12 Kbytes Page:10 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

74F109SC产品属性

  • 类型

    描述

  • 型号

    74F109SC

  • 功能描述

    触发器 Dual J-K Flip-Flop

  • RoHS

  • 制造商

    Texas Instruments

  • 电路数量

    2

  • 逻辑系列

    SN74

  • 逻辑类型

    D-Type Flip-Flop

  • 极性

    Inverting, Non-Inverting

  • 输入类型

    CMOS

  • 传播延迟时间

    4.4 ns

  • 高电平输出电流

    - 16 mA

  • 低电平输出电流

    16 mA

  • 电源电压-最大

    5.5 V

  • 最大工作温度

    + 85 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    X2SON-8

  • 封装

    Reel

更新时间:2025-8-11 20:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
FAIRCHILD/仙童
24+
NA/
2500
优势代理渠道,原装正品,可全系列订货开增值税票
FAIRCHILD
24+/25+
2000
原装正品现货库存价优
FAIRCHILD
1815+
SOP16-3.9MM
6528
只做原装正品现货!或订货,假一赔十!
FSC/ON
23+
原包装原封 □□
18368
原装进口特价供应 特价,原装元器件供应,支持开发样品 更多详细咨询 库存
FAIR
9924
16SOIC
300
一级代理,专注军工、汽车、医疗、工业、新能源、电力
FAIR
22+
SOP16
25000
只做原装进口现货,专注配单
FAIR
25+23+
SOP16
22174
绝对原装正品全新进口深圳现货
FAI
24+
1056
原厂
2020+
1632
百分百原装正品 真实公司现货库存 本公司只做原装 可
FCS
24+
3.9mm
2987
只售原装自家现货!诚信经营!欢迎来电!

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