Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo

封装/外壳：14-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：袋 描述：IC FF JK TYPE DUAL 1BIT 14DIP 集成电路（IC） 触发器

Dual J-K negative edge-triggered flip-flops without reset

DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo

Dual J-K negative edge-triggered flip-flops without reset

DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level

Dual J-K negative edge-triggered flip-flops without reset

DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level

Dual J-K negative edge-triggered flip-flops without reset

DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level