位置：首页 > IC中文资料第7661页 > 74F112
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
丝印代码：74F112；DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t | TI 德州仪器 |   | ||
丝印代码：74F112；DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t | TI 德州仪器 | | ||
74F112 | Dual J-K negative edge-triggered flip-flop DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level | PHILIPS 飞利浦 | | |
74F112 | Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | FAIRCHILD 仙童半导体 | | |
74F112 | Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | |
74F112 | Dual JK Negative Edge-Triggered Flip-Flop | ONSEMI 安森美半导体 | | |
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | FAIRCHILD 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | FAIRCHILD 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | FAIRCHILD 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FAIRCHILD 仙童半导体 | | ||
Dual J-K negative edge-triggered flip-flop DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level | PHILIPS 飞利浦 | | ||
Dual J-K negative edge-triggered flip-flop DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level | PHILIPS 飞利浦 | | ||
Dual J-K negative edge-triggered flip-flop DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level | PHILIPS 飞利浦 | | ||
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET 文件：73.2 Kbytes Page：5 Pages | TI 德州仪器 | | ||
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET 文件：73.2 Kbytes Page：5 Pages | TI 德州仪器 | |
74F112产品属性
- 类型
描述
- 型号
74F112
- 制造商
FAIRCHILD
- 制造商全称
Fairchild Semiconductor
- 功能描述
Dual JK Negative Edge-Triggered Flip-Flop
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI/德州仪器 |
25+ |
原厂封装 |
10280 |
原厂授权代理,专注军工、汽车、医疗、工业、新能源！ |
|||
TI/德州仪器 |
23+ |
SOP |
5000 |
全新原装,支持实单,非诚勿扰 |
|||
TI(德州仪器) |
25+ |
SOP16208mil |
2886 |
原装现货,免费供样,技术支持,原厂对接 |
|||
TI |
23+ |
SOP |
8560 |
受权代理!全新原装现货特价热卖! |
|||
TI/德州仪器 |
23+ |
SOP |
3200 |
公司只做原装，可来电咨询 |
|||
ADI |
23+ |
SOP16-5.2 |
8000 |
只做原装现货 |
|||
ADI |
23+ |
SOP16-5.2 |
7000 |
||||
TI/德州仪器 |
25+ |
SOP-16 |
30000 |
公司只有原装 |
|||
TI/德州仪器 |
25+ |
原厂封装 |
10280 |
||||
TI/德州仪器 |
22+ |
SOP-16 |
20000 |
公司只有原装 品质保障 |
74F112规格书下载地址
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74F112数据表相关新闻
74F14SCX原装现货，价格美丽
74F14SCX原装现货，价格美丽
2024-7-1174F08M，74F1016DW，74F109D，74F109DR，74F109N，74F10D，
74F08M，74F1016DW，74F109D，74F109DR，74F109N，74F10D，
2020-2-1774F00SCX公司原装现货随时可以发货
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74F00SCX
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74FCT245ATSOC
2019-3-4
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