位置：首页 > IC中文资料第7661页 > 74F112
| 型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
|---|---|---|---|---|
74F112 | Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 |   | |
74F112 | Dual J-K negative edge-triggered flip-flop DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level | Philips 飞利浦 | | |
74F112 | Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | |
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
Dual JK Negative Edge-Triggered Flip-Flop 文件：83.34 Kbytes Page：7 Pages | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | |
74F112产品属性
- 类型
描述
- 型号
74F112
- 制造商
FAIRCHILD
- 制造商全称
Fairchild Semiconductor
- 功能描述
Dual JK Negative Edge-Triggered Flip-Flop
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
onsemi(安森美) |
24+ |
SOP16 |
1583 |
只做原装,提供一站式配单服务,代工代料。BOM配单 |
|||
FUJITSU/富士通 |
24+ |
NA/ |
506 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
TI |
23+ |
NA |
20000 |
全新原装假一赔十 |
|||
NS |
22+23+ |
SOP16 |
8000 |
新到现货，只做原装进口 |
|||
NS |
25+ |
SOP-16 |
65428 |
百分百原装现货 实单必成 |
|||
NS |
06+ |
SOP16 |
45 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
PHI |
25+ |
SOP |
3200 |
全新原装、诚信经营、公司现货销售 |
|||
FAIRCHILD/仙童 |
24+ |
SOP3.9 |
128 |
大批量供应优势库存热卖 |
|||
FAI |
24+ |
SOP3.9 |
20000 |
一级代理原装现货假一罚十 |
|||
恩XP |
1715+ |
SOP |
251156 |
只做原装正品现货假一赔十! |
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74F112规格书下载地址
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74F112数据表相关新闻
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2024-7-1174F08M，74F1016DW，74F109D，74F109DR，74F109N，74F10D，
74F08M，74F1016DW，74F109D，74F109DR，74F109N，74F10D，
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74FCT245ATSOC
2019-3-4
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