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CY7C256价格
参考价格：￥1375.1627
型号：CY7C2562XV18-450BZXC 品牌：Cynergy 3 备注：这里有CY7C256多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C256批发/采购报价，CY7C256行情走势销售排行榜，CY7C256报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR® II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | Infineon 英飞凌 | | ||
Synchronous SRAM | Infineon 英飞凌 | | ||
封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 72MBIT PARALLEL 165FBGA 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C256产品属性
- 类型
描述
- 型号
CY7C256
- 功能描述
静态随机存取存储器 72MB(4Mx18) 1.8v 366MHz QDR II 静态随机存取存储器
- RoHS
否
- 制造商
Cypress Semiconductor
- 存储容量
16 Mbit
- 组织
1 M x 16
- 访问时间
55 ns
- 电源电压-最大
3.6 V
- 电源电压-最小
2.2 V
- 最大工作电流
22 uA
- 最大工作温度
+ 85 C
- 最小工作温度
- 40 C
- 安装风格
SMD/SMT
- 封装/箱体
TSOP-48
- 封装
Tray
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Cypress(赛普拉斯) |
24+ |
NA/ |
8735 |
原厂直销,现货供应,账期支持! |
|||
CYPRESS |
ROHS+Original |
NA |
1221 |
专业电子元器件供应链/QQ 350053121 /正纳电子 |
|||
CYPRESS/赛普拉斯 |
20+ |
FBGA-165 |
1360 |
||||
CYPRESS/赛普拉斯 |
20+ |
FBGA-165 |
1 |
进口原装现货假一赔万力挺实单 |
|||
CYPRESS |
22+ |
BGA |
8000 |
原装正品支持实单 |
|||
INFINEON/英飞凌 |
23+ |
P-BGA-165 |
28611 |
为终端用户提供优质元器件 |
|||
Cypress |
25+ |
25000 |
原厂原包 深圳现货 主打品牌 假一赔百 可开票! |
||||
Cypress Semiconductor Corp |
25+ |
165-LBGA |
9350 |
独立分销商 公司只做原装 诚心经营 免费试样正品保证 |
|||
Cypress |
Cypress专业分销 |
3200 |
Cypress一级分销,原装原盒原包装! |
||||
CYPRESS |
17+ |
BGA |
60000 |
保证进口原装可开17%增值税发票 |
CY7C256规格书下载地址
CY7C256参数引脚图相关
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DdatasheetPDF页码索引
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