Quad And/Or Select Gate

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Description CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each con sist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter.  

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters(Dual Clock With Reset)

Features • CD40192BMS - BCD Type • CD40193BMS - Binary Type • High Voltage Type (20V Rating) • Individual Clock Lines for Counting Up or Counting Down • Synchronous High-Speed Carry and Borrow Propagation Delays for Cascading • Asynchronous Reset and Preset Capability • Medium Speed Operat

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Description CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each con sist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter.  

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Description CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each con sist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter.  

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters(Dual Clock With Reset)

Features • CD40192BMS - BCD Type • CD40193BMS - Binary Type • High Voltage Type (20V Rating) • Individual Clock Lines for Counting Up or Counting Down • Synchronous High-Speed Carry and Borrow Propagation Delays for Cascading • Asynchronous Reset and Preset Capability • Medium Speed Operat

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Description CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each con sist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter.  

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS 4-Bit Bidirectional Universal Shift Register

Features: 8 Medium-speed: CL. = 12 MHz typ) @ Vdd = 10v Fully static operation Synchronous parallel or serial operation Asynchronous master reset Standardized, symmetrical output characteristics 5V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC

CMOS 4-Bit Bidirectional Universal Shift Register

Features: 8 Medium-speed: CL. = 12 MHz typ) @ Vdd = 10v Fully static operation Synchronous parallel or serial operation Asynchronous master reset Standardized, symmetrical output characteristics 5V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC

CMOS 4-Bit Bidirectional Universal Shift Register

Features: 8 Medium-speed: CL. = 12 MHz typ) @ Vdd = 10v Fully static operation Synchronous parallel or serial operation Asynchronous master reset Standardized, symmetrical output characteristics 5V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC

CMOS 4-Bit Bidirectional Universal Shift Register

Description The CD40104BMS is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a high impedance third output state allowing the device to be used in bus organized systems. In the parallel load mode (S0 and S1 are high), dat

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

Quad AND-OR Select Gate

General Description The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These comple mentary MOS (CMOS) transistors provide the building blocks

Quad AND-OR Select Gate

General Description The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These comple mentary MOS (CMOS) transistors provide the building blocks

Quad AND-OR Select Gate

General Description The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These comple mentary MOS (CMOS) transistors provide the building blocks

Quad AND-OR Select Gate

General Description The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These comple mentary MOS (CMOS) transistors provide the building blocks

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quad AND/OR Select Gate

Description CD4019BMS types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits ca

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

QUAD AND/OR SELECT GATE

Quadruple 2-input multiplexer

Quadruple 2-input multiplexer

4-Bit AND/OR Selector or Quad 2-Channel Data Selector or Quad Exclusive nor gate

COMPLEMENTARY METAL OXIDE SILICON

C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC