CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOs Presettable Up/Down counters

文件：1.11003 Mbytes Page：15 Pages

CMOS PRESETTABLE UP/DOWN COUNTERS(DUAL CLOCK WITH RESET)

文件：516.35 Kbytes Page：11 Pages

CMOS Pressettable Up/Down Counters

文件：1.11213 Mbytes Page：16 Pages

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 包装：管件 描述：IC UP/DOWN COUNTR PRESET 16SO 集成电路（IC） 计数器，除法器

Synchronous 4-Bit Up/Down Decade Counter . Synchronous 4-Bit Up/Down Binary Counter

General Description The CD40192BC and CD40193BC up/down counters are monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the CD40193BC is a binary counter. Counting up and counting down is performed by two count inputs, one being held HIGH while the othe

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Description CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each con sist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter.  

Synchronous 4-Bit Up/Down Decade Counter

文件：141.69 Kbytes Page：6 Pages

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Features: Individual clock lines for counting up or counting down Synchronous high-speed carry and borrow propagation delays for cascading Asynchronous reset and preset capability Medium-speed operation—fcy = 8 MHz (typ) @ 10 V 5.V, 10-V, and 15-V parametric ratings Standardized, symmetrica

CMOS Pressettable Up/Down Counters

文件：1.11213 Mbytes Page：16 Pages

CMOS Pressettable Up/Down Counters

文件：1.11213 Mbytes Page：16 Pages

CMOS PRESETTABLE UP/DOWN COUNTERS(DUAL CLOCK WITH RESET)

文件：516.35 Kbytes Page：11 Pages

CMOs Presettable Up/Down counters

文件：1.11003 Mbytes Page：15 Pages