位置:CD40192BNSR.A > CD40192BNSR.A详情

CD40192BNSR.A中文资料

厂家型号

CD40192BNSR.A

文件大小

915.5Kbytes

页面数量

20

功能描述

CMOS Presettable Up/Down Counters (Dual Clock With Reset)

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

CD40192BNSR.A数据手册规格书PDF详情

Features:

Individual clock lines for counting up or counting down

Synchronous high-speed carry and borrow propagation

delays for cascading

Asynchronous reset and preset capability

Medium-speed operation—fcy = 8 MHz (typ) @ 10 V

5.V, 10-V, and 15-V parametric ratings

Standardized, symmetrical output

characteristics

100% tested for quiescent current at 20 V

Maximum input current of 1 uA at 18 V

over full package temperature range; 100 i

“nA at 18 Vand 25°C

Noise margin over full package temperature

range:

1VatVpp=5V 2VatVpp=10V

25VatVpp=15V

Meets all requirements of JEDEC Tentative

Standard No. 13B, “Standard Specifications

for Description of ‘B’ Series CMOS Devices”

更新时间:2025-10-7 10:01:00
供应商 型号 品牌 批号 封装 库存 备注 价格
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