CMOS 4-Bit Bidirectional Universal Shift Register

Features: 8 Medium-speed: CL. = 12 MHz typ) @ Vdd = 10v Fully static operation Synchronous parallel or serial operation Asynchronous master reset Standardized, symmetrical output characteristics 5V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC

CMOS 4 位双向通用移位寄存器

CD40194B is a universal shift register featuring parallel inputs, parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive • Medium-speed: fCL = 12 MHz (typ.) @ VDD = 10 V\n• Synchronous parallel or serial operation\n• Standardized, symmetrical output characteristics\n• Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"\n• Serial/parallel co;

CMOS 4-BIT BIDIRECTIONAL UNLVERSAL SHIFT REGISTER

文件：342.33 Kbytes Page：9 Pages

CMOS 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

文件：233.64 Kbytes Page：7 Pages

丝印代码：CD40194BE；CMOS 4-Bit Bidirectional Universal Shift Register

Features: 8 Medium-speed: CL. = 12 MHz typ) @ Vdd = 10v Fully static operation Synchronous parallel or serial operation Asynchronous master reset Standardized, symmetrical output characteristics 5V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC

丝印代码：CD40194BE；CMOS 4-Bit Bidirectional Universal Shift Register

Features: 8 Medium-speed: CL. = 12 MHz typ) @ Vdd = 10v Fully static operation Synchronous parallel or serial operation Asynchronous master reset Standardized, symmetrical output characteristics 5V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC

CMOS 4-Bit Bidirectional Universal Shift Register

Description The CD40104BMS is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a high impedance third output state allowing the device to be used in bus organized systems. In the parallel load mode (S0 and S1 are high), dat

CMOS 4-BIT BIDIRECTIONAL UNLVERSAL SHIFT REGISTER

文件：342.33 Kbytes Page：9 Pages

CMOS 4-BIT BIDIRECTIONAL UNLVERSAL SHIFT REGISTER

文件：342.33 Kbytes Page：9 Pages

CMOS 4-Bit Bidirectional Universal Shift Register

文件：342.33 Kbytes Page：9 Pages

CMOS 4-BIT BIDIRECTIONAL UNLVERSAL SHIFT REGISTER

文件：342.33 Kbytes Page：9 Pages

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 功能：通用 包装：管件 描述：IC 4BIT BI-DIR SHIFT REG 16SO 集成电路（IC） 移位寄存器

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 功能：通用 包装：管件 描述：IC 4BIT BI-DIR SHIFT REG 16SO 集成电路（IC） 移位寄存器

4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

DESCRIPTION The HCC40104B, HCC40194B, (extended temperature range) and the HCC40104B, HCF40194B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF 40104B is a universal shift regi

4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

DESCRIPTION The HCC40104B, HCC40194B, (extended temperature range) and the HCC40104B, HCF40194B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF 40104B is a universal shift regi

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

4-bit Bidirectional Universal Shift Register

4-bit bidirectional universal shift register

4-bit bidirectional universal shift register

4-bit bidirectional universal shift register

4-Bit Bidirectional Universal Shift Register

4-Bit Bidirectional Universal Shift Register