丝印代码：CD4019B；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019B；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS 四路与/或选择门

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

丝印代码：CD4019BE；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BE；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BE；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BF；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BF；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BF3A；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BF3A；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BM；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BM；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BM；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CD4019BM；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

Quad AND-OR Select Gate

General Description The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These comple mentary MOS (CMOS) transistors provide the building blocks

Quad AND-OR Select Gate

General Description The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These comple mentary MOS (CMOS) transistors provide the building blocks

Quad AND-OR Select Gate

General Description The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These comple mentary MOS (CMOS) transistors provide the building blocks

Quad AND-OR Select Gate

General Description The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These comple mentary MOS (CMOS) transistors provide the building blocks

CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quad AND/OR Select Gate

Description CD4019BMS types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits ca

丝印代码：CM019B；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

丝印代码：CM019B；CMOS Quaa AND/OR Select Gate High-Voltage Types (20-Volt Rating)

Features: 8 Medium-speed operation... .. + -tpHL = tp Ly = 60 ns (typ.) at C) =50pF,Vpp=10V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 138, “S

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

Quad AND-OR Select Gate

文件：107.97 Kbytes Page：4 Pages

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC QUAD AND/OR SELECT GATE 16DIP 集成电路（IC） 门和反相器 - 多功能，可配置

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 包装：卷带（TR） 描述：IC QUAD AND/OR SELECT GATE 16DIP 集成电路（IC） 门和反相器 - 多功能，可配置

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

Quad AND-OR Select Gate

文件：107.97 Kbytes Page：4 Pages

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

CMOS 四路与/或选择门

CMOS Quad AND/OR Select Gate

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

CMOS Quad AND/OR Select Gate

文件：515.929 Kbytes Page：11 Pages

CMOS Quad AND/OR Gate

文件：938.29 Kbytes Page：16 Pages

EPDM Snap-In Liquid Tight Bushings

文件：95.85 Kbytes Page：1 Pages

US-100 Ultrasonic Distance Sensor - 3V or 5V Logic

文件：490.95 Kbytes Page：3 Pages

VALVES TRIODES

文件：147.04 Kbytes Page：4 Pages

EPDM Snap-In Liquid Tight Bushings

文件：95.85 Kbytes Page：1 Pages

VALVES TRIODES

文件：147.04 Kbytes Page：4 Pages

QUAD AND/OR SELECT GATE

Quadruple 2-input multiplexer

Quadruple 2-input multiplexer

4-Bit AND/OR Selector or Quad 2-Channel Data Selector or Quad Exclusive nor gate

COMPLEMENTARY METAL OXIDE SILICON

C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC