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CY7C25价格
参考价格：￥1628.8263
型号：CY7C25442KV18-300BZI 品牌：Cynergy 3 备注：这里有CY7C25多少钱，2026年最近7天走势，今日出价，今日竞价，CY7C25批发/采购报价，CY7C25行情走势销售排行榜，CY7C25报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C25 | 256/512/1K/2K/4K x 9 Asynchronous FIFO 文件：622.02 Kbytes Page：17 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2562XV18 and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Functional Description The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has d | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：835.39 Kbytes Page：26 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR® II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT | INFINEON 英飞凌 | | ||
72-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：751.97 Kbytes Page：28 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
Synchronous SRAM | INFINEON 英飞凌 | | ||
72-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：751.97 Kbytes Page：28 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：751.97 Kbytes Page：28 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 72MBIT PARALLEL 165FBGA 集成电路（IC） 存储器 | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
Synchronous SRAM | INFINEON 英飞凌 | | ||
72-Mbit QDR짰II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：835.39 Kbytes Page：26 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：741.25 Kbytes Page：28 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：741.25 Kbytes Page：28 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 72MBIT PARALLEL 165FBGA 集成电路（IC） 存储器 | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：741.25 Kbytes Page：28 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：741.25 Kbytes Page：28 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：835.39 Kbytes Page：26 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：835.39 Kbytes Page：26 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：835.39 Kbytes Page：26 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR짰II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 文件：835.39 Kbytes Page：26 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
72-Mbit QDR-II SRAM 4-Word Burst Architecture 文件：845.88 Kbytes Page：29 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C25产品属性
- 类型
描述
- 型号
CY7C25
- 制造商
Rochester Electronics LLC
- 功能描述
- Bulk
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS |
23+ |
FBGA165 |
668 |
优势渠道,百分之百货源稳定,欢迎来电咨询83972189 |
|||
CYPRESS/赛普拉斯 |
25+ |
BGA |
12496 |
CYPRESS/赛普拉斯原装正品CY7C25702KV18即刻询购立享优惠#长期有货 |
|||
CYPRESS/赛普拉斯 |
24+ |
CWDIP |
1145 |
原装优势现货 |
|||
CYPRESS |
24+ |
BGA |
8540 |
只做原装正品现货或订货假一赔十! |
|||
CYPRESS/赛普拉斯 |
25+ |
BGA |
12500 |
全新原装现货,假一赔十 |
|||
CYPRESS/赛普拉斯 |
25+ |
SMD |
918000 |
明嘉莱只做原装正品现货 |
|||
CYPRESS |
24+ |
BGA |
9860 |
全新原装现货/假一罚百! |
|||
CYPRESS/赛普拉斯 |
2025+ |
DIP |
4850 |
原装进口价格优 请找坤融电子! |
|||
CY |
20+ |
DIP |
3242 |
英卓尔科技,进口原装现货! |
|||
Cypress Semiconductor Corp |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
CY7C25芯片相关品牌
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DdatasheetPDF页码索引
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