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SCAN价格
参考价格：￥41.6943
型号：SCAN15MB200TSQ/NOPB 品牌：TI 备注：这里有SCAN多少钱，2025年最近7天走势，今日出价，今日竞价，SCAN批发/采购报价，SCAN行情走势销售排行榜，SCAN报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 FEATURES • 1.5 Gbps Data Rate Per Channel • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs • Low Output Skew and Jitter • On-chip 100Ω Input and Output Termination • IEEE 1149.1 and 1149.6 Compliant • | TI 德州仪器 |   | ||
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 FEATURES • 1.5 Gbps Data Rate Per Channel • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs • Low Output Skew and Jitter • On-chip 100Ω Input and Output Termination • IEEE 1149.1 and 1149.6 Compliant • | TI 德州仪器 | | ||
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 FEATURES • 1.5 Gbps Data Rate Per Channel • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs • Low Output Skew and Jitter • On-chip 100Ω Input and Output Termination • IEEE 1149.1 and 1149.6 Compliant • | TI 德州仪器 | | ||
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 FEATURES • 1.5 Gbps Data Rate Per Channel • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs • Low Output Skew and Jitter • On-chip 100Ω Input and Output Termination • IEEE 1149.1 and 1149.6 Compliant • | TI 德州仪器 | | ||
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 FEATURES • 1.5 Gbps Data Rate Per Channel • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs • Low Output Skew and Jitter • On-chip 100Ω Input and Output Termination • IEEE 1149.1 and 1149.6 Compliant • | TI 德州仪器 | | ||
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 FEATURES • 1.5 Gbps Data Rate Per Channel • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs • Low Output Skew and Jitter • On-chip 100Ω Input and Output Termination • IEEE 1149.1 and 1149.6 Compliant • | TI 德州仪器 | | ||
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 FEATURES • 1.5 Gbps Data Rate Per Channel • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs • Low Output Skew and Jitter • On-chip 100Ω Input and Output Termination • IEEE 1149.1 and 1149.6 Compliant • | TI 德州仪器 | | ||
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 FEATURES • 1.5 Gbps Data Rate Per Channel • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs • Low Output Skew and Jitter • On-chip 100Ω Input and Output Termination • IEEE 1149.1 and 1149.6 Compliant • | TI 德州仪器 | | ||
Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6 FEATURES • 1.5 Gbps Data Rate Per Channel • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs • Low Output Skew and Jitter • On-chip 100Ω Input and Output Termination • IEEE 1149.1 and 1149.6 Compliant • | TI 德州仪器 | | ||
Non-Inverting Transceiver with 25ohm Series Resistor Outputs General Description The SCAN182245A is a high performance BiCMOS bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundar | Fairchild 仙童半导体 | | ||
Non-Inverting Transceiver with 25ohm Series Resistor Outputs General Description The SCAN182245A is a high performance BiCMOS bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundar | Fairchild 仙童半导体 | | ||
Non-Inverting Transceiver with 25ohm Series Resistor Outputs General Description The SCAN182245A is a high performance BiCMOS bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundar | Fairchild 仙童半导体 | | ||
Transparent Latch with 25ohm Series Resistor Outputs General Description The SCAN182373A is a high performance BiCMOS transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Sca | Fairchild 仙童半导体 | | ||
Transparent Latch with 25ohm Series Resistor Outputs General Description The SCAN182373A is a high performance BiCMOS transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Sca | Fairchild 仙童半导体 | | ||
Transparent Latch with 25ohm Series Resistor Outputs General Description The SCAN182373A is a high performance BiCMOS transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Sca | Fairchild 仙童半导体 | | ||
D-Type Flip-Flop with 25廓 Series Resistor Outputs General Description The SCAN182374A is a high performance BiCMOS D-type flip-flop featuring separate D-type inputs organized into dual 9-bit bytes with byte-oriented clock and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Arch | Fairchild 仙童半导体 | | ||
D-Type Flip-Flop with 25廓 Series Resistor Outputs General Description The SCAN182374A is a high performance BiCMOS D-type flip-flop featuring separate D-type inputs organized into dual 9-bit bytes with byte-oriented clock and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Arch | Fairchild 仙童半导体 | | ||
Non-Inverting Transceiver with 3-STATE Outputs General Description The SCAN18245T is a high speed, low-power bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary S | Fairchild 仙童半导体 | | ||
Non-Inverting Transceiver with 3-STATE Outputs General Description The SCAN18245T is a high speed, low-power bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary S | Fairchild 仙童半导体 | | ||
Non-Inverting Line Driver with 25ohm Series Resistor Outputs General Description The SCAN182541A is a high performance BiCMOS line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Scan architecture w | Fairchild 仙童半导体 | | ||
Non-Inverting Line Driver with 25ohm Series Resistor Outputs General Description The SCAN182541A is a high performance BiCMOS line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Scan architecture w | Fairchild 仙童半导体 | | ||
Non-Inverting Line Driver with 25ohm Series Resistor Outputs General Description The SCAN182541A is a high performance BiCMOS line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary-Scan architecture w | Fairchild 仙童半导体 | | ||
Transparent Latch with 3-STATE Outputs General Description The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan A | Fairchild 仙童半导体 | | ||
D-Type Flip-Flop with 3-STATE Outputs General Description The SCAN18374T is a high speed, low-power D-type flip-flop featuring separate D-type inputs organized into dual 9-bit bytes with byte-oriented clock and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and BOUNDARY-SCAN Archite | Fairchild 仙童半导体 | | ||
D-Type Flip-Flop with 3-STATE Outputs General Description The SCAN18374T is a high speed, low-power D-type flip-flop featuring separate D-type inputs organized into dual 9-bit bytes with byte-oriented clock and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and BOUNDARY-SCAN Archite | Fairchild 仙童半导体 | | ||
Transparent Latch with 3-STATE Outputs General Description The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan A | Fairchild 仙童半导体 | | ||
Inverting Line Driver with 3-STATE Outputs General Description The SCAN18540T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with | Fairchild 仙童半导体 | | ||
Inverting Line Driver with 3-STATE Outputs General Description The SCAN18540T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with | Fairchild 仙童半导体 | | ||
Non-Inverting Line Driver with 3-STATE Outputs General Description The SCAN18541T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with | Fairchild 仙童半导体 | | ||
Non-Inverting Line Driver with 3-STATE Outputs General Description The SCAN18541T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with | Fairchild 仙童半导体 | | ||
SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis 1FEATURES 2• 1.5 Gbps Maximum Data Rate Per Channel • Configurable Pre-emphasis Drives Lossy Backplanes and Cables • Low Output Skew and Jitter • LVDS/CML/LVPECL Compatible Input, LVDS Output • On-chip 100Ω Input and Output Termination • 12 kV ESD Protection on LVDS Outputs • IEEE 1149.1 | TI 德州仪器 | | ||
SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis 1FEATURES 2• 1.5 Gbps Maximum Data Rate Per Channel • Configurable Pre-emphasis Drives Lossy Backplanes and Cables • Low Output Skew and Jitter • LVDS/CML/LVPECL Compatible Input, LVDS Output • On-chip 100Ω Input and Output Termination • 12 kV ESD Protection on LVDS Outputs • IEEE 1149.1 | TI 德州仪器 | | ||
SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis 1FEATURES 2• 1.5 Gbps Maximum Data Rate Per Channel • Configurable Pre-emphasis Drives Lossy Backplanes and Cables • Low Output Skew and Jitter • LVDS/CML/LVPECL Compatible Input, LVDS Output • On-chip 100Ω Input and Output Termination • 12 kV ESD Protection on LVDS Outputs • IEEE 1149.1 | TI 德州仪器 | | ||
SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis 1FEATURES 2• 1.5 Gbps Maximum Data Rate Per Channel • Configurable Pre-emphasis Drives Lossy Backplanes and Cables • Low Output Skew and Jitter • LVDS/CML/LVPECL Compatible Input, LVDS Output • On-chip 100Ω Input and Output Termination • 12 kV ESD Protection on LVDS Outputs • IEEE 1149.1 | TI 德州仪器 | | ||
SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis 1FEATURES 2• 1.5 Gbps Maximum Data Rate Per Channel • Configurable Pre-emphasis Drives Lossy Backplanes and Cables • Low Output Skew and Jitter • LVDS/CML/LVPECL Compatible Input, LVDS Output • On-chip 100Ω Input and Output Termination • 12 kV ESD Protection on LVDS Outputs • IEEE 1149.1 | TI 德州仪器 | | ||
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 1FEATURES 2• 1.5 Gbps per Channel • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps • Low Output Jitter • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations • F | TI 德州仪器 | | ||
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 1FEATURES 2• 1.5 Gbps per Channel • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps • Low Output Jitter • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations • F | TI 德州仪器 | | ||
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 1FEATURES 2• 1.5 Gbps per Channel • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps • Low Output Jitter • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations • F | TI 德州仪器 | | ||
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 1FEATURES 2• 1.5 Gbps per Channel • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps • Low Output Jitter • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations • F | TI 德州仪器 | | ||
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 1FEATURES 2• 1.5 Gbps per Channel • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps • Low Output Jitter • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations • F | TI 德州仪器 | | ||
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 1FEATURES 2• 1.5 Gbps per Channel • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps • Low Output Jitter • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations • F | TI 德州仪器 | | ||
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 1FEATURES 2• 1.5 Gbps per Channel • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps • Low Output Jitter • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations • F | TI 德州仪器 | | ||
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 1FEATURES 2• 1.5 Gbps per Channel • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps • Low Output Jitter • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations • F | TI 德州仪器 | | ||
SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6 1FEATURES 2• 1.5 Gbps per Channel • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps • Low Output Jitter • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations • F | TI 德州仪器 | | ||
SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode. • Clock Recovery From PLL Lock to Random Data Patterns. • Specified Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode. • Clock Recovery From PLL Lock to Random Data Patterns. • Specified Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode. • Clock Recovery From PLL Lock to Random Data Patterns. • Specified Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode. • Clock Recovery From PLL Lock to Random Data Patterns. • Specified Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | | ||
SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST 1FEATURES 2• IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode. • Clock Recovery From PLL Lock to Random Data Patterns. • Specified Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption | TI 德州仪器 | |
SCAN产品属性
- 类型
描述
- 型号
SCAN
- 制造商
NSC
- 制造商全称
National Semiconductor
- 功能描述
1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
三年内 |
1983 |
只做原装正品 |
||||
TI(德州仪器) |
24+ |
QFN-48-EP(7x7) |
7969 |
支持大陆交货,美金交易。原装现货库存。 |
|||
TI/德州仪器 |
23+ |
48-WQFN |
3940 |
原装正品代理渠道价格优势 |
|||
24+ |
N/A |
70000 |
一级代理-主营优势-实惠价格-不悔选择 |
||||
Texas Instruments(德州仪器) |
24+ |
SOIC-8 |
690000 |
代理渠道/支持实单/只做原装 |
|||
TI |
16+ |
WQFN |
10000 |
原装正品 |
|||
Texas Instruments |
24+ |
48-WQFN(7x7) |
56300 |
一级代理/放心采购 |
|||
TI/德州仪器 |
25+ |
原厂封装 |
10280 |
||||
NS |
24+ |
原厂封装 |
65250 |
支持样品,原装现货,提供技术支持! |
|||
TI/德州仪器 |
25+ |
WQFN-48 |
860000 |
明嘉莱只做原装正品现货 |
SCAN规格书下载地址
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- SCAN90CP02SP/NOPB
- SCAN90004TVS/NOPB
- SCAN15MB200TSQ/NOPB
- SCALEONLYFOR8508
- SCAJ6F
- SCAJ6
- SCAJ4F
- SCAJ4
- SCAJ2F
- SCAJ2
- SCAJ1F
- SCAJ05F
- SCA90CA
- SCA90AA
- SCA8X0
- SCA85CA
- SCA830-D07-PCB
- SCA830-D07-1
- SCA830-D06-PCB
- SCA830-D06-1
- SCA830-D05-1
- SCA820-D04-1
- SCA78CA
- SCA75CA
- SCA70CA
- SCA70AA
- SCA-7
- SCA6X0
- SCA64CA
- SCA630-EDCV1B-1
- SCA630
- SCA620-EF1V1B-1
- SCA61T-FAHH1G-1
- SCA61T-FA1H1G-1
- SCA610-E28H1A-1
- SCA610-E23H1A-1
- SCA600AC0-16B
- SCA600AC0-16A
- SCA3100-D07-1
- SCA3100-D04DEMO
- SCA3100-D04-1
- SCA3060-D01-1
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