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型号	功能描述	生产厂家企业	LOGO
PLL102-10	Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the	PLL	PLL
PLL102-108	Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose	PLL	PLL
PLL102-108XC	Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose	PLL	PLL
PLL102-108XI	Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose	PLL	PLL
PLL102-108XM	Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose	PLL	PLL
PLL102-109	Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose	PLL	PLL
PLL102-109XC	Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose	PLL	PLL
PLL102-109XI	Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose	PLL	PLL
PLL102-109XM	Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose	PLL	PLL
PLL102-10SC	Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the	PLL	PLL
PLL102-10SC-R	Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the	PLL	PLL
PLL102-108XC	Programmable DDR Zero Delay Clock Driver	PLL	PLL
PLL102-109XI	Programmable DDR Zero Delay Clock Driver	PLL	PLL
P102-10SC	Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the	PLL	PLL
HVI102-10	UNIVERSAL INPUT AC-DC OPEN FRAME SINGLE & MULTI-OUTPUT 100 WATTS INTERNAL SWITCHING POWER SUPPLIES 文件：361.06 Kbytes Page：2 Pages	HITRON 仲琦科技	HITRON
PL102-10	Low Skew Output Buffer 文件：287.78 Kbytes Page：7 Pages	Micrel 麦瑞半导体	Micrel
PL102-10SC	Low Skew Output Buffer 文件：287.78 Kbytes Page：7 Pages	Micrel 麦瑞半导体	Micrel
PL102-10SC-R	Low Skew Output Buffer 文件：287.78 Kbytes Page：7 Pages	Micrel 麦瑞半导体	Micrel

PLL102-10产品属性

类型
描述
型号
PLL102-10
制造商
PLL
制造商全称
PLL
功能描述
Low Skew Output Buffer

PLL102-10供应商更多...

更新时间：2025-12-31 23:01:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市得捷芯城科技有限公司	PLL103-02XC	PHASELIN	24+	NA/	30	优势代理渠道,原装正品,可全系列订货开增值税票	询价
深圳市纳艾斯科技有限公司	PLL103-02XC	PHASELI	24+	SSOP48	8000	只做自己库存全新原装进口正品假一赔百可开13%增	询价
深圳市威雅利发展有限公司	PLL103-02XC	PHASELIN	0350+	SSOP48	30	一级代理,专注军工、汽车、医疗、工业、新能源、电力	询价
千层芯半导体(深圳)有限公司	PLL1045A	ZCOMM	24+	SMD	1680	ZCOMM专营品牌进口原装现货假一赔十	询价
深圳市振宏微科技有限公司	PLL103-02XC		23+	BGAQFP	8659	原装公司现货!原装正品价格优势.	询价
深圳市创新迹电子有限公司	PLL103-02XC	PHASELIN	22+	SSOP48	20000	公司只做原装品质保障	询价
深圳市华斯顿科技有限公司	PLL103-02XC	PHASELINK	25+23+	SSOP	36452	绝对原装正品全新进口深圳现货	询价
深圳诚思涵科技有限公司	PLL103-02XC		16+	FBGA	4000	进口原装现货/价格优势!	询价
深圳市壹芯创科技有限公司	PLL103-02XC	PHASELIN	22+	SSOP48	5000	全新原装现货!自家库存!	询价
深圳市一线半导体有限公司	PLL102-109XC		24+		3000	公司存货	询价

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PLL102-10产品属性

PLL102-10供应商更多...

PLL102-10芯片相关品牌

PLL102-10规格书下载地址

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PLL102-10数据表相关新闻

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PLED13Q12全新原装特价现货出售

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PLUS16L8-7N，PLUS16L8DN，PLUS16R4-7N，PLUS16R4DN，PLUS20L8-7N，

PL4054

PM2071LED单段线性驱动芯片

DdatasheetPDF页码索引