Buffers

The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of t • Frequency Range:\n• 15 to 145MHz @ 2.5V\n• Zero Input to Output Delay\n• Less Than 200ps Skew Between Outputs\n• 2.5V or 3.3V Power Supply\n• Available in 8-Pin SOP or 6-pin SOT GREEN/ RoHS Compliant Packages;

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER 1:3 170MHZ 8SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages

封装/外壳：SOT-23-6 包装：卷带（TR） 描述：IC CLK BUFFER 1:3 170MHZ 6SOT23 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages

Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

UNIVERSAL INPUT AC-DC OPEN FRAME SINGLE & MULTI-OUTPUT 100 WATTS INTERNAL SWITCHING POWER SUPPLIES

文件：361.06 Kbytes Page：2 Pages