型号 功能描述 生产厂家 企业 LOGO 操作
PLL102-109XC

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

PLL102-109XC产品属性

  • 类型

    描述

  • 型号

    PLL102-109XC

  • 制造商

    PLL

  • 制造商全称

    PLL

  • 功能描述

    Programmable DDR Zero Delay Clock Driver

更新时间:2025-11-22 11:01:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
PHASELI
2447
SSOP48
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
PHASELINK
23+
SSOP
50000
全新原装正品现货,支持订货
PHASELINK
25+23+
SSOP
36452
绝对原装正品全新进口深圳现货
PHASELIN
23+
SSOP48
2530
原厂原装正品
24+
3000
公司存货
PHASELIN
22+
SSOP48
5000
全新原装现货!自家库存!
PHASELIN
23+
SSOP48
30
全新原装正品现货,支持订货
PHASELIN
0350+
SSOP48
30
普通
PHASELIN
0350+
SSOP48
30
一级代理,专注军工、汽车、医疗、工业、新能源、电力
PLL
23+
SSOP
360000
原厂授权一级代理,专业海外优势订货,价格优势、品种

PLL102-109XC数据表相关新闻