型号 功能描述 生产厂家 企业 LOGO 操作
PLL102-109XC

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

PLL102-109XC产品属性

  • 类型

    描述

  • 型号

    PLL102-109XC

  • 制造商

    PLL

  • 制造商全称

    PLL

  • 功能描述

    Programmable DDR Zero Delay Clock Driver

更新时间:2026-3-2 23:55:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
PHASELIN
0350+
SSOP48
30
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PHASELI
24+
SSOP48
8000
只做自己库存 全新原装进口正品假一赔百 可开13%增
PHASELIN
20+
TSSOP8
2960
诚信交易大量库存现货
23+
BGAQFP
8659
原装公司现货!原装正品价格优势.
ZCOMM
24+
SMD
1680
ZCOMM专营品牌进口原装现货假一赔十
PHASELINK
25+23+
SSOP
36452
绝对原装正品全新进口深圳现货
PHASELI
25+
SSOP48
30
百分百原装正品 真实公司现货库存 本公司只做原装 可
PHASELIN
22+
SSOP48
5000
全新原装现货!自家库存!
25+
SSOP
2700
全新原装自家现货优势!
PHASELIN
0350+
SSOP48
30

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