Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

Low Skew Output Buffer

DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the

UNIVERSAL INPUT AC-DC OPEN FRAME SINGLE & MULTI-OUTPUT 100 WATTS INTERNAL SWITCHING POWER SUPPLIES

文件：361.06 Kbytes Page：2 Pages

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages

Low Skew Output Buffer

文件：287.78 Kbytes Page：7 Pages