型号 功能描述 生产厂家 企业 LOGO 操作
PLL102-108XM

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

Programmable DDR Zero Delay Clock Driver

DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose

PLL

PLL102-108XM产品属性

  • 类型

    描述

  • 型号

    PLL102-108XM

  • 制造商

    PLL

  • 制造商全称

    PLL

  • 功能描述

    Programmable DDR Zero Delay Clock Driver

更新时间:2025-10-6 23:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
PHASELIN
24+
NA/
30
优势代理渠道,原装正品,可全系列订货开增值税票
PHASELI
24+
SSOP48
8000
只做自己库存 全新原装进口正品假一赔百 可开13%增
23+
BGAQFP
8659
原装公司现货!原装正品价格优势.
PHASELINK
25+23+
SSOP
36452
绝对原装正品全新进口深圳现货
24+
3000
公司存货
16+
FBGA
4000
进口原装现货/价格优势!
PHASELI
2447
SSOP48
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
ZCOMM
24+
SMD
1680
ZCOMM专营品牌进口原装现货假一赔十
KHATOD
25+
光电元件
982
就找我吧!--邀您体验愉快问购元件!
PHASELIN
0350+
SSOP48
30
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