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位置：首页 > IC中文资料第4757页 > MK20

MK20价格

参考价格：￥266.0990

型号：MK20 品牌：HELLERMANN 备注：这里有MK20多少钱，2026年最近7天走势，今日出价，今日竞价，MK20批发/采购报价，MK20行情走势销售排行榜，MK20报价。

型号	功能描述	生产厂家企业	LOGO
MK20	MK20/1 Series Reed Sensors Features: Cylindrical Reed Sensor, Choice of Cable Termination & Lengths available, Various Case Sizes Applications: Door & Window Contacts, With Magnetic Floats for Water Level Detection, Position Sensing	STANDEX	STANDEX
MK2011	Fast Ethernet Clock Source Description The MK2011 is the ideal way to generate clocks for Fast Ethernet cards or systems. It provides 20MHz, 25MHz, and 50MHz clocks. In an 8 pin SOIC, the MK2011 can save component count, board space, and cost over surface mount crystals and oscillators, and increase reliability by eliminat	ICST	ICST
MK2011S	Fast Ethernet Clock Source Description The MK2011 is the ideal way to generate clocks for Fast Ethernet cards or systems. It provides 20MHz, 25MHz, and 50MHz clocks. In an 8 pin SOIC, the MK2011 can save component count, board space, and cost over surface mount crystals and oscillators, and increase reliability by eliminat	ICST	ICST
MK2011STR	Fast Ethernet Clock Source Description The MK2011 is the ideal way to generate clocks for Fast Ethernet cards or systems. It provides 20MHz, 25MHz, and 50MHz clocks. In an 8 pin SOIC, the MK2011 can save component count, board space, and cost over surface mount crystals and oscillators, and increase reliability by eliminat	ICST	ICST
MK2014A	Fast Ethernet Clock Source Description The MK2014A is the ideal way to generate clocks for Fast Ethernet cards or systems. It provides 20MHz and 25MHz clocks from an inexpensive 14.31818 MHz crystal or clock. In an 8 pin SOIC, the MK2014A can save component count, board space, and cost over surface mount crystals and oscil	ICST	ICST
MK2014ATR	Fast Ethernet Clock Source Description The MK2014A is the ideal way to generate clocks for Fast Ethernet cards or systems. It provides 20MHz and 25MHz clocks from an inexpensive 14.31818 MHz crystal or clock. In an 8 pin SOIC, the MK2014A can save component count, board space, and cost over surface mount crystals and oscil	ICST	ICST
MK2042-01	Communications Clock Monitor Description The MK2042-01 is designed to switch between two clock sources. The switching can be externally controlled by an input pin or configured to switch automatically if the primary input clock stops. The part also provides clock detection by reporting when the primary input clock has stoppe	ICST	ICST
MK2042-01SI	Communications Clock Monitor Description The MK2042-01 is designed to switch between two clock sources. The switching can be externally controlled by an input pin or configured to switch automatically if the primary input clock stops. The part also provides clock detection by reporting when the primary input clock has stoppe	ICST	ICST
MK2042-01SITR	Communications Clock Monitor Description The MK2042-01 is designed to switch between two clock sources. The switching can be externally controlled by an input pin or configured to switch automatically if the primary input clock stops. The part also provides clock detection by reporting when the primary input clock has stoppe	ICST	ICST
MK2049-01	Communications Clock PLL Description The MK2049 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference and generates T1, E1, T3, E3, and OC3 frequencies. The device can also accept a T1, E1, T3, or E3 input clock and provide the same output for loop timing. All outputs are	ICST	ICST
MK2049-01S	Communications Clock PLL Description The MK2049 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference and generates T1, E1, T3, E3, and OC3 frequencies. The device can also accept a T1, E1, T3, or E3 input clock and provide the same output for loop timing. All outputs are	ICST	ICST
MK2049-01SI	Communications Clock PLL Description The MK2049 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference and generates T1, E1, T3, E3, and OC3 frequencies. The device can also accept a T1, E1, T3, or E3 input clock and provide the same output for loop timing. All outputs are	ICST	ICST
MK2049-01SITR	Communications Clock PLL Description The MK2049 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference and generates T1, E1, T3, E3, and OC3 frequencies. The device can also accept a T1, E1, T3, or E3 input clock and provide the same output for loop timing. All outputs are	ICST	ICST
MK2049-01STR	Communications Clock PLL Description The MK2049 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference and generates T1, E1, T3, E3, and OC3 frequencies. The device can also accept a T1, E1, T3, or E3 input clock and provide the same output for loop timing. All outputs are	ICST	ICST
MK2049-02	Communications Clock PLLs Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation	ICST	ICST
MK2049-02S	Communications Clock PLLs Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation	ICST	ICST
MK2049-02SI	Communications Clock PLLs Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation	ICST	ICST
MK2049-02SITR	Communications Clock PLLs Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation	ICST	ICST
MK2049-02STR	Communications Clock PLLs Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation	ICST	ICST
MK2049-03S	Communications Clock PLLs Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation	ICST	ICST
MK2049-03SI	Communications Clock PLLs Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation	ICST	ICST
MK2049-03SITR	Communications Clock PLLs Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation	ICST	ICST
MK2049-03STR	Communications Clock PLLs Description The MK2049-02 and MK2049-03 are Phase-Locked Loop (PLL) based clock synthesizers that accept multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-02/03 generate T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation	ICST	ICST
MK2049-34	3.3 V Communications Clock PLL Description The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clocks freq	ICST	ICST
MK2049-34	3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Fixed I/O phase relationship on all selections • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8	RENESAS 瑞萨	RENESAS
MK2049-34A	3.3 Volt Communications Clock VCXO PLL Description The MK2049-34A is a VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clo	ICST	ICST
MK2049-34SAI	3.3 Volt Communications Clock VCXO PLL Description The MK2049-34A is a VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clo	ICST	ICST
MK2049-34SAITR	3.3 Volt Communications Clock VCXO PLL Description The MK2049-34A is a VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clo	ICST	ICST
MK2049-34SI	3.3 V Communications Clock PLL Description The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clocks freq	ICST	ICST
MK2049-34SI	3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Fixed I/O phase relationship on all selections • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8	RENESAS 瑞萨	RENESAS
MK2049-34SITR	3.3 V Communications Clock PLL Description The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies. This allows for the generation of clocks freq	ICST	ICST
MK2049-34SITR	3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Fixed I/O phase relationship on all selections • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8	RENESAS 瑞萨	RENESAS
MK2049-35	3.3 V Communications Clock PLL Description The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o	ICST	ICST
MK2049-35SI	3.3 V Communications Clock PLL Description The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o	ICST	ICST
MK2049-35SITR	3.3 V Communications Clock PLL Description The MK2049-35 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-35 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o	ICST	ICST
MK2049-36	3.3 V Communications Clock PLL Description The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o	ICST	ICST
MK2049-36	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20 pin SOIC • Pb (lead) free package • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock or	RENESAS 瑞萨	RENESAS
MK2049-36SI	3.3 V Communications Clock PLL Description The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o	ICST	ICST
MK2049-36SILF	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20 pin SOIC • Pb (lead) free package • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock or	RENESAS 瑞萨	RENESAS
MK2049-36SILFTR	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20 pin SOIC • Pb (lead) free package • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock or	RENESAS 瑞萨	RENESAS
MK2049-36SITR	3.3 V Communications Clock PLL Description The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies. This allows for the generation o	ICST	ICST
MK2049-45	3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.	ICST	ICST
MK2049-45	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to	RENESAS 瑞萨	RENESAS
MK2049-45A	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to	RENESAS 瑞萨	RENESAS
MK2049-45ASILF	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to	RENESAS 瑞萨	RENESAS
MK2049-45ASILFTR	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to	RENESAS 瑞萨	RENESAS
MK2049-45SI	3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.	ICST	ICST
MK2049-45SI	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to	RENESAS 瑞萨	RENESAS
MK2049-45SILF	3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.	ICST	ICST
MK2049-45SILF	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to	RENESAS 瑞萨	RENESAS
MK2049-45SILFTR	3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.	ICST	ICST
MK2049-45SILFTR	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to	RENESAS 瑞萨	RENESAS
MK2049-45SITR	3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication.	ICST	ICST
MK2049-45SITR	3.3 VOLT COMMUNICATIONS CLOCK PLL Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to	RENESAS 瑞萨	RENESAS
MK2058-01	Communications Clock Jitter Attenuator Description The MK2058-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module	ICST	ICST
MK2058-01	COMMUNICATIONS CLOCK JITTER ATTENUATOR Features • Excellent jitter attenuation for telecom clocks • Also serves as a general purpose clock jitter attenuator for distributed system clocks and recovered data or video clocks • 2:1 Input MUX for input reference clocks • No switching glitches on output • VCXO-based clock generation o	RENESAS 瑞萨	RENESAS
MK2058-01SI	Communications Clock Jitter Attenuator Description The MK2058-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module	ICST	ICST
MK2058-01SILF	COMMUNICATIONS CLOCK JITTER ATTENUATOR Features • Excellent jitter attenuation for telecom clocks • Also serves as a general purpose clock jitter attenuator for distributed system clocks and recovered data or video clocks • 2:1 Input MUX for input reference clocks • No switching glitches on output • VCXO-based clock generation o	RENESAS 瑞萨	RENESAS
MK2058-01SILFTR	COMMUNICATIONS CLOCK JITTER ATTENUATOR Features • Excellent jitter attenuation for telecom clocks • Also serves as a general purpose clock jitter attenuator for distributed system clocks and recovered data or video clocks • 2:1 Input MUX for input reference clocks • No switching glitches on output • VCXO-based clock generation o	RENESAS 瑞萨	RENESAS
MK2058-01SITR	Communications Clock Jitter Attenuator Description The MK2058-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module	ICST	ICST

MK20产品属性

类型
描述
型号
MK20
制造商
HellermannTyton
功能描述
Bulk
制造商
HellermannTyton
功能描述
INSTALLATION TOOL PLASTIC
制造商
HellermannTyton
功能描述
INSTALLATION TOOL, PLASTIC
制造商
HELLERMANN TYTON
功能描述
INSTALLATION TOOL, PLASTIC;
SVHC
No SVHC(19-Dec-2012); Accessory
Type
Cable Management Tools; External
Length/Height
170mm; For Use
With
Cable Ties;
Material
Plastic ;RoHS
Compliant
NA
制造商
PCTEL
功能描述
ANTENNA HARDWARE/ACCESSORY

MK20供应商更多...

更新时间：2026-1-27 23:00:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市高捷芯城科技有限公司	MK20DX256ZVLQ10	恩XP	24+	标准封装	27048	全新原装正品/价格优惠/质量保障	询价
深圳市振宏微科技有限公司	MK2018KFE	ROEDERSTE	23+	NA	4008	专做原装正品,假一罚百!	询价
千层芯半导体(深圳)有限公司	MK20/1-B-100W	MEDERelectronic	24+	原厂原装	6000	进口原装正品假一赔十,货期7-10天	询价
芯有半导体（深圳）有限公司	MK201R5FER	ROE	05+	原厂原装	50051	只做全新原装真实现货供应	询价
深圳市宏世佳电子科技有限公司	MK2014S	ICS	2025+	SOP8	4816	全新原厂原装产品、公司现货销售	询价
深圳市得捷芯城科技有限公司	MK20DX256ZVLK10	Freescale(飞思卡尔)	25+	标准封装	7751	我们只是原厂的搬运工	询价
深圳诚思涵科技有限公司	MK20DX256VMD10	FREESCALE	24+	BGA	32350	深圳存库原装现货	询价
深圳市赛特兴科技有限公司	MK200-281515	INTERPOINT	QQ咨询	189-8877-7135	68	全新原装研究所指定供货商	询价
深圳市一线半导体有限公司	MK200-281515		24+		5000	公司存货	询价
深圳市能元时代电子有限公司	MK200-281515	INTERPOINT	23+	模块	12800	公司只有原装欢迎来电咨询。	询价

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