MK20价格

参考价格:¥266.0990

型号:MK20 品牌:HELLERMANN 备注:这里有MK20多少钱,2024年最近7天走势,今日出价,今日竞价,MK20批发/采购报价,MK20行情走势销售排行榜,MK20报价。
型号 功能描述 生产厂家&企业 LOGO 操作

Fast Ethernet Clock Source

Description TheMK2011istheidealwaytogenerateclocksforFastEthernetcardsorsystems.Itprovides20MHz,25MHz,and50MHzclocks.Inan8pinSOIC,theMK2011cansavecomponentcount,boardspace,andcostoversurfacemountcrystalsandoscillators,andincreasereliabilitybyeliminat

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Fast Ethernet Clock Source

Description TheMK2011istheidealwaytogenerateclocksforFastEthernetcardsorsystems.Itprovides20MHz,25MHz,and50MHzclocks.Inan8pinSOIC,theMK2011cansavecomponentcount,boardspace,andcostoversurfacemountcrystalsandoscillators,andincreasereliabilitybyeliminat

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Fast Ethernet Clock Source

Description TheMK2011istheidealwaytogenerateclocksforFastEthernetcardsorsystems.Itprovides20MHz,25MHz,and50MHzclocks.Inan8pinSOIC,theMK2011cansavecomponentcount,boardspace,andcostoversurfacemountcrystalsandoscillators,andincreasereliabilitybyeliminat

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Fast Ethernet Clock Source

Description TheMK2014AistheidealwaytogenerateclocksforFastEthernetcardsorsystems.Itprovides20MHzand25MHzclocksfromaninexpensive14.31818MHzcrystalorclock.Inan8pinSOIC,theMK2014Acansavecomponentcount,boardspace,andcostoversurfacemountcrystalsandoscil

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Fast Ethernet Clock Source

Description TheMK2014AistheidealwaytogenerateclocksforFastEthernetcardsorsystems.Itprovides20MHzand25MHzclocksfromaninexpensive14.31818MHzcrystalorclock.Inan8pinSOIC,theMK2014Acansavecomponentcount,boardspace,andcostoversurfacemountcrystalsandoscil

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Communications Clock Monitor

Description TheMK2042-01isdesignedtoswitchbetweentwoclocksources.Theswitchingcanbeexternallycontrolledbyaninputpinorconfiguredtoswitchautomaticallyiftheprimaryinputclockstops.Thepartalsoprovidesclockdetectionbyreportingwhentheprimaryinputclockhasstoppe

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Communications Clock Monitor

Description TheMK2042-01isdesignedtoswitchbetweentwoclocksources.Theswitchingcanbeexternallycontrolledbyaninputpinorconfiguredtoswitchautomaticallyiftheprimaryinputclockstops.Thepartalsoprovidesclockdetectionbyreportingwhentheprimaryinputclockhasstoppe

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Communications Clock Monitor

Description TheMK2042-01isdesignedtoswitchbetweentwoclocksources.Theswitchingcanbeexternallycontrolledbyaninputpinorconfiguredtoswitchautomaticallyiftheprimaryinputclockstops.Thepartalsoprovidesclockdetectionbyreportingwhentheprimaryinputclockhasstoppe

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Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

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Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

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Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

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Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

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Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

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Communications Clock PLLs

Description TheMK2049-02andMK2049-03arePhase-LockedLoop(PLL)basedclocksynthesizersthatacceptmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-02/03generateT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegeneration

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Communications Clock PLLs

Description TheMK2049-02andMK2049-03arePhase-LockedLoop(PLL)basedclocksynthesizersthatacceptmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-02/03generateT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegeneration

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Communications Clock PLLs

Description TheMK2049-02andMK2049-03arePhase-LockedLoop(PLL)basedclocksynthesizersthatacceptmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-02/03generateT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegeneration

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Communications Clock PLLs

Description TheMK2049-02andMK2049-03arePhase-LockedLoop(PLL)basedclocksynthesizersthatacceptmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-02/03generateT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegeneration

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Communications Clock PLLs

Description TheMK2049-02andMK2049-03arePhase-LockedLoop(PLL)basedclocksynthesizersthatacceptmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-02/03generateT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegeneration

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Communications Clock PLLs

Description TheMK2049-02andMK2049-03arePhase-LockedLoop(PLL)basedclocksynthesizersthatacceptmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-02/03generateT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegeneration

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Communications Clock PLLs

Description TheMK2049-02andMK2049-03arePhase-LockedLoop(PLL)basedclocksynthesizersthatacceptmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-02/03generateT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegeneration

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Communications Clock PLLs

Description TheMK2049-02andMK2049-03arePhase-LockedLoop(PLL)basedclocksynthesizersthatacceptmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-02/03generateT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegeneration

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Communications Clock PLLs

Description TheMK2049-02andMK2049-03arePhase-LockedLoop(PLL)basedclocksynthesizersthatacceptmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-02/03generateT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegeneration

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3.3 V Communications Clock PLL

Description TheMK2049-34isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-34generatesT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegenerationofclocksfreq

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3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features •Packagedin20-pinSOIC •3.3V+5operation •FixedI/Ophaserelationshiponallselections •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8

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3.3 Volt Communications Clock VCXO PLL

Description TheMK2049-34AisaVCXOPhasedLockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-34AgeneratesT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegenerationofclo

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3.3 Volt Communications Clock VCXO PLL

Description TheMK2049-34AisaVCXOPhasedLockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-34AgeneratesT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegenerationofclo

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3.3 Volt Communications Clock VCXO PLL

Description TheMK2049-34AisaVCXOPhasedLockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-34AgeneratesT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegenerationofclo

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3.3 V Communications Clock PLL

Description TheMK2049-34isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-34generatesT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegenerationofclocksfreq

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3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features •Packagedin20-pinSOIC •3.3V+5operation •FixedI/Ophaserelationshiponallselections •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8

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3.3 V Communications Clock PLL

Description TheMK2049-34isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-34generatesT1,E1,T3,E3,ISDN,xDSL,andothercommunicationsfrequencies.Thisallowsforthegenerationofclocksfreq

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3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features •Packagedin20-pinSOIC •3.3V+5operation •FixedI/Ophaserelationshiponallselections •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8

RENESASRenesas Electronics America

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3.3 V Communications Clock PLL

Description TheMK2049-35isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-35generatesT1,E1,T3,E3,OC3/3,GigabitEthernet,andothercommunicationsfrequencies.Thisallowsforthegenerationo

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3.3 V Communications Clock PLL

Description TheMK2049-35isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-35generatesT1,E1,T3,E3,OC3/3,GigabitEthernet,andothercommunicationsfrequencies.Thisallowsforthegenerationo

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3.3 V Communications Clock PLL

Description TheMK2049-35isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-35generatesT1,E1,T3,E3,OC3/3,GigabitEthernet,andothercommunicationsfrequencies.Thisallowsforthegenerationo

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3.3 V Communications Clock PLL

Description TheMK2049-36isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-36generatesT1,E1,T3,E3,OC3/3,GigabitEthernet,andothercommunicationsfrequencies.Thisallowsforthegenerationo

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3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •Pb(lead)freepackage •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclockor

RENESASRenesas Electronics America

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RENESAS

3.3 V Communications Clock PLL

Description TheMK2049-36isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-36generatesT1,E1,T3,E3,OC3/3,GigabitEthernet,andothercommunicationsfrequencies.Thisallowsforthegenerationo

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ICST

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •Pb(lead)freepackage •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclockor

RENESASRenesas Electronics America

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3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •Pb(lead)freepackage •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclockor

RENESASRenesas Electronics America

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3.3 V Communications Clock PLL

Description TheMK2049-36isaPhase-LockedLoop(PLL)basedclocksynthesizerthatacceptsmultipleinputfrequencies.Withan8kHzclockinputasareference,theMK2049-36generatesT1,E1,T3,E3,OC3/3,GigabitEthernet,andothercommunicationsfrequencies.Thisallowsforthegenerationo

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3.3V Communications Clock PLL

Description TheMK2049-45isadualPhase-LockedLoop(PLL)devicewhichcanprovidefrequencysynthesisandjitterattenuation.ThefirstPLLisVCXObasedandusesapullablecrystaltotracksignalwanderandattenuateinputjitter.ThesecondPLLisatranslatorforfrequencymultiplication.

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3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclock,or10to 50MHz •Locksto

RENESASRenesas Electronics America

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RENESAS

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20-pinSOIC •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclock,or10to 50MHz •Locksto

RENESASRenesas Electronics America

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RENESAS

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20-pinSOIC •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclock,or10to 50MHz •Locksto

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3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20-pinSOIC •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclock,or10to 50MHz •Locksto

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3.3V Communications Clock PLL

Description TheMK2049-45isadualPhase-LockedLoop(PLL)devicewhichcanprovidefrequencysynthesisandjitterattenuation.ThefirstPLLisVCXObasedandusesapullablecrystaltotracksignalwanderandattenuateinputjitter.ThesecondPLLisatranslatorforfrequencymultiplication.

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3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclock,or10to 50MHz •Locksto

RENESASRenesas Electronics America

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RENESAS

3.3V Communications Clock PLL

Description TheMK2049-45isadualPhase-LockedLoop(PLL)devicewhichcanprovidefrequencysynthesisandjitterattenuation.ThefirstPLLisVCXObasedandusesapullablecrystaltotracksignalwanderandattenuateinputjitter.ThesecondPLLisatranslatorforfrequencymultiplication.

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3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclock,or10to 50MHz •Locksto

RENESASRenesas Electronics America

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RENESAS

3.3V Communications Clock PLL

Description TheMK2049-45isadualPhase-LockedLoop(PLL)devicewhichcanprovidefrequencysynthesisandjitterattenuation.ThefirstPLLisVCXObasedandusesapullablecrystaltotracksignalwanderandattenuateinputjitter.ThesecondPLLisatranslatorforfrequencymultiplication.

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ICST

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclock,or10to 50MHz •Locksto

RENESASRenesas Electronics America

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RENESAS

3.3V Communications Clock PLL

Description TheMK2049-45isadualPhase-LockedLoop(PLL)devicewhichcanprovidefrequencysynthesisandjitterattenuation.ThefirstPLLisVCXObasedandusesapullablecrystaltotracksignalwanderandattenuateinputjitter.ThesecondPLLisatranslatorforfrequencymultiplication.

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ICST

3.3 VOLT COMMUNICATIONS CLOCK PLL

Features •Packagedin20pinSOIC •3.3V+5operation •MeetstheTR62411,ETS300011,andGR-1244 specificationforMTIE,Pull-in/Hold-inRange,Phase Transients,andJitterGenerationforStratum3,4,and4E •Acceptsmultipleinputs:8kHzbackplaneclock,or10to 50MHz •Locksto

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Communications Clock Jitter Attenuator

Description TheMK2058-01isaVCXO(VoltageControlledCrystalOscillator)basedclockjitterattenuatordesignedforsystemclockdistributionapplications.ThismonolithicIC,combinedwithanexternalinexpensivequartzcrystal,canbeusedtoreplaceamorecostlyhybridVCXOretimingmodule

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COMMUNICATIONS CLOCK JITTER ATTENUATOR

Features •Excellentjitterattenuationfortelecomclocks •Alsoservesasageneralpurposeclockjitterattenuator fordistributedsystemclocksandrecovereddataorvideo clocks •2:1InputMUXforinputreferenceclocks •Noswitchingglitchesonoutput •VCXO-basedclockgenerationo

RENESASRenesas Electronics America

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RENESAS

Communications Clock Jitter Attenuator

Description TheMK2058-01isaVCXO(VoltageControlledCrystalOscillator)basedclockjitterattenuatordesignedforsystemclockdistributionapplications.ThismonolithicIC,combinedwithanexternalinexpensivequartzcrystal,canbeusedtoreplaceamorecostlyhybridVCXOretimingmodule

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COMMUNICATIONS CLOCK JITTER ATTENUATOR

Features •Excellentjitterattenuationfortelecomclocks •Alsoservesasageneralpurposeclockjitterattenuator fordistributedsystemclocksandrecovereddataorvideo clocks •2:1InputMUXforinputreferenceclocks •Noswitchingglitchesonoutput •VCXO-basedclockgenerationo

RENESASRenesas Electronics America

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COMMUNICATIONS CLOCK JITTER ATTENUATOR

Features •Excellentjitterattenuationfortelecomclocks •Alsoservesasageneralpurposeclockjitterattenuator fordistributedsystemclocksandrecovereddataorvideo clocks •2:1InputMUXforinputreferenceclocks •Noswitchingglitchesonoutput •VCXO-basedclockgenerationo

RENESASRenesas Electronics America

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RENESAS

Communications Clock Jitter Attenuator

Description TheMK2058-01isaVCXO(VoltageControlledCrystalOscillator)basedclockjitterattenuatordesignedforsystemclockdistributionapplications.ThismonolithicIC,combinedwithanexternalinexpensivequartzcrystal,canbeusedtoreplaceamorecostlyhybridVCXOretimingmodule

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华润微电子华润微电子有限公司

ICST

VCXO-Based Frame Clock Frequency Translator

Description TheMK2059-01isaVCXO(VoltageControlledCrystalOscillator)basedclockgeneratorthatproducescommontelecommunicationsreferencefrequencies.Theoutputclockisphaselockedtoan8kHz(framerate)inputreferenceclock.TheMK2059-01alsoprovidesjitterattenuation. Featur

ICSTChina Resources Microelectronics Limited Limited

华润微电子华润微电子有限公司

ICST

MK20产品属性

  • 类型

    描述

  • 型号

    MK20

  • 制造商

    HellermannTyton

  • 功能描述

    Bulk

  • 制造商

    HellermannTyton

  • 功能描述

    INSTALLATION TOOL PLASTIC

  • 制造商

    HellermannTyton

  • 功能描述

    INSTALLATION TOOL, PLASTIC

  • 制造商

    HELLERMANN TYTON

  • 功能描述

    INSTALLATION TOOL, PLASTIC;

  • SVHC

    No SVHC(19-Dec-2012); Accessory

  • Type

    Cable Management Tools; External

  • Length/Height

    170mm; For Use

  • With

    Cable Ties;

  • Material

    Plastic ;RoHS

  • Compliant

    NA

  • 制造商

    PCTEL

  • 功能描述

    ANTENNA HARDWARE/ACCESSORY

更新时间:2024-5-10 22:30:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ROEDERSTEIN
2020+
NA
80000
只做自己库存,全新原装进口正品假一赔百,可开13%增
ICS
2016+
SOP8
6528
只做进口原装现货!假一赔十!
ROEDERSTE
23+
NA
4008
专做原装正品,假一罚百!
MK
2023+
SMD28
3000
进口原装现货
ICS
SOP8
68900
原包原标签100%进口原装常备现货!
ICS
21+
SOP8
20000
原厂订货价格优势,可开13%的增值税票
ROE
05+
原厂原装
50051
只做全新原装真实现货供应
5000
公司存货
MICROCLO
23+
SOP
1057
ICS
2023+
SOP8
4816
全新原厂原装产品、公司现货销售

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