Features

• Packaged in 20-pin SOIC

• 3.3 V + 5 operation

• Fixed I/O phase relationship on all selections

• Meets the TR62411, ETS300 011, and GR-1244

specification for MTIE, Pull-in/Hold-in Range, Phase

Transients, and Jitter Generation for Stratum 3, 4, and 4E

• Accepts multiple inputs: 8 kHz backplane clock, Loop

Timing frequencies, or 10 to 36 MHz

• Locks to 8 kHz + 100 ppm (External mode)

• Buffer Mode allows jitter attenuation of 10 to 36 MHz

input and x1/x0.5 or x2/x4 outputs

• Exact internal ratios enable zero ppm error

• Output clock rates include T1, E1, T3, E3, ISDN, xDSL,

and the OC3 submultiples

• See also the MK2049-36 and MK2049-45