3M Scotch-Weld Metal Instant Adhesive MC100

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8-BIT SYNCHRONOUS BINARY UP COUNTER

Description The MC10E/100E016 is a high−speed synchronous, presettable, cascadable 8−bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H™ family, extended to 8−bits, as shown in the logic symbol. Features • 700 MHz Min. Count Frequency • 1000 ps CLK

QUAD 4-INPUT OR/NOR GATE

The MC10E/100E101 is a quad 4-input OR/NOR gate. • 500ps Max. Propagation Delay • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors

5V ECL Quad 4짯Input OR/NOR Gate

Description The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7

5V ECL Quad 4짯Input OR/NOR Gate

Description The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7

5V ECL Quad 4짯Input OR/NOR Gate

Description The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7

QUINT 2-INPUT AND/NAND GATE

Description The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used. The 100 Series contains temperature compensation. Features • 600 ps Max. P

QUINT 2-INPUT XOR/XNOR GATE

Description The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used. The 100 Series contains temperature compensation. Features • 600 ps Maximum Pr

1:9 DIFFERENTIAL CLOCK DRIVER

Description The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable i

QUAD DRIVER

Description The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock driver, although the M

QUINT DIFFERENTIAL LINE RECEIVER

Description The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest. Active current sources plus a deep collector feature of the MOSAIC III process provide t

9-BIT BUFFER

Description The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting buffer gates. The 100 Series contains temperature compensation. Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC =

4-BIT D FLIP-FLOP

Description The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved by holding the CE inputs LOW and using CC to

6-BIT UNIVERSAL UP/DOWN COUNTER

Description The MC10E/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry output and accepts a look-ahead-carry input. These two features allow for the cascading of multiple E136’s for wider bit width counters that operate at very nea

8-BIT RIPPLE COUNTER

Description The MC10E/100E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLinPS™ output edge rates. This allows the counter to operate at very high frequencies while maintain

8-BIT SHIFT REGISTER

Description The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0 − D7 accept parallel input data, while DL/DR accept serial input data for left/right shifting. The Qn outputs do

9-BIT SHIFT REGISTER

Description The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 − D8 accept parallel input data, while S-IN accepts serial input data. The Qn output

9-BIT HOLD REGISTER

Description The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 − D8 accepting parallel input data. The SEL (Select) input pin is used to switch between the two modes of operation −

6-BIT D LATCH

Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset

6-BIT D REGISTER

Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs g

5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

6-BIT 2:1 MUX-LATCH

Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

3-BIT 4:1 MUX-LATCH

Description The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LE

QUAD 2:1 MULTIPLEXER

The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. • Individual Select Controls • 550ps Max. D to Output • 80

QUAD 2:1 MULTIPLEXER

Description The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. The 100 Series contains temperature compensation.

QUAD 2:1 MULTIPLEXER

The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. • Individual Select Controls • 550ps Max. D to Output • 80

QUAD 2:1 MULTIPLEXER

The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs. • Individual Select Controls • 550ps Max. D to Output • 80

5-BIT 2:1 MULTIPLEXER

Description The MC10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input (SEL). The 100 Series contains temperature compensation. Features • 600 ps Max. D to Output • 800 ps Max. SEL to Output • Differential Outputs • One VCC

12-BIT PARITY GENERATOR/CHECKER

The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The 100 Series contains temperature compensation. • Provides Odd-HIGH Parity of 12 Inputs • Shiftable Output Register with

2-BIT 8:1 MULTIPLEXER

Description The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs (SEL0, 1, 2) control which one of the eight data inputs (A0 − A7, B0 − B7) is propagated to the output. The 100 Series contains temperature compensation. Features •

16:1 MULTIPLEXER

Description The MC10E/100E164 is a 16:1 multiplexer with a differential output. The select inputs (SEL0, 1, 2, 3 ) control which one of the sixteen data inputs (A0 − A15) is propagated to the output. Special attention to the design layout results in a typical skew between the 16 inputs of only 5

9-BIT MAGNITUDE COMPARATOR

Description The MC10E/100E166 is a 9-bit magnitude comparator which compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other. The 100 Series contains temperature compensation Features • 1100 ps Max. A = B • PECL Mode Operating Range:

6-BIT 2:1 MUX-REGISTER

Description The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (

3-BIT 4:1 MULTIPLEXER

Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs (see logic symbol). The three Select inputs control which one of the four data inputs in each case is propagated to the corresponding output

9-BIT LATCH WITH PARITY

Description The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type se

ERROR DETECTION/ CORRECTION CIRCUIT

The MC10E/100E193 is an error detection and correction (EDAC) circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also provided at the PGEN pin, after Odd/Even

PROGRAMMABLE DELAY CHIP

Description The MC10E/100E195 is a programmable delay chip (PDC) designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic symbol. The first two

PROGRAMMABLE DELAY CHIP

Description The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elem

5V ECL Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

5V ECL Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

5V ECL Dual 1:4, 1:5 Differential Fanout Buffer

Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features f

1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP

The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The 100 Series contains temperature compensation. • Guaranteed Low Skew Specification • Synchronous Enabling/Disabling • Multiplexed Clock Inputs • VBB Output for Single-Ended U

3-BIT SCANNABLE REGISTERED ADDRESS DRIVER

The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed

8-BIT SCANABLE REGISTER

5V ECL 8-Bit Scannable Register The MC10E/100E241 is an 8-bit shiftable register. Unlike a standard universal shift register such as the E141, the E241 features internal data feedback organized so that the SHIFT control overrides the HOLD/LOAD control. This enables the normal operations of HOLD a

3-BIT 4:1 MUX-LATCH

The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol). When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the m

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

3-BIT REGISTERED BUS TRANSCEIVER

The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs (BUS0–BUS2) are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW,

3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER

The MC10E/100E337 is a 3-bit registered bus transceiver with scan. The bus outputs (BUS0–BUS2) are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW, the outputs go to – 2.0 V

QUAD DIFFERENTIAL AND/NAND

The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level gate inputs. T

QUAD DIFFERENTIAL AND/NAND

The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level gate inputs. T

QUAD DIFFERENTIAL AND/NAND

The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level gate inputs. T

QUINT DIFFERENTIAL LINE RECEIVER

Description The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The design incorporates two stages of gain, internal to the device, making it an ex

3-BIT DIFFERENTIAL FLIP-FLOP

Description The MC10E/100E431 is a 3-bit flip-flop with differential clock, data input and data output. The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock