9-BIT LATCH WITH PARITY

Description The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type se

5V ECL 9-Bit Latch With Parity

文件：81.24 Kbytes Page：8 Pages

9-BIT LATCH WITH PARITY

5V ECL 9-Bit Latch With Parity

文件：81.24 Kbytes Page：8 Pages

5V ECL 9-Bit Latch With Parity

文件：81.24 Kbytes Page：8 Pages

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC LATCH 9BIT PARITY ECL 28-PLCC 集成电路（IC） 锁存器

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC LATCH 9BIT PARITY ECL 28-PLCC 集成电路（IC） 锁存器

5V ECL 9-Bit Latch With Parity

文件：81.24 Kbytes Page：8 Pages

5V ECL 9-Bit Latch With Parity

文件：81.24 Kbytes Page：8 Pages

9-BIT LATCH WITH PARITY

DESCRIPTION The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type s