5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

5V ECL 5-Bit 2:1 Mux-Latch

文件：127.21 Kbytes Page：8 Pages

5V ECL 5-Bit 2:1 Mux-Latch

文件：127.21 Kbytes Page：8 Pages

5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

5-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E154 offer five 2:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external Latch-Enable signals (LEN1, LEN2) are gated through a logical OR operation before use as control for the five latches. Wh

5-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E154 offer five 2:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external Latch-Enable signals (LEN1, LEN2) are gated through a logical OR operation before use as control for the five latches. Wh

5-BIT 2:1 MUX-LATCH

文件：63.08 Kbytes Page：4 Pages