6-BIT D REGISTER

Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs g

MC100E151: ECL 6-Bit D Flip-Flop Register

The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs go LOW.The 100 S 1100MHz Min. Toggle Frequency\nDifferential Outputs\nAsynchronous Master Reset\nDualClocks\nPECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\nNECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\nInternal Input Pulldown Resistors\nESD Protection: > 2 kV HBM, > 200 V MM\nMee;

5V ECL 6-Bit D Register

文件：127.84 Kbytes Page：8 Pages

5V ECL 6-Bit D Register

文件：127.84 Kbytes Page：8 Pages

5V ECL 6-Bit D Register

文件：127.84 Kbytes Page：8 Pages

5V ECL 6?륛it D Register

文件：155.48 Kbytes Page：7 Pages

包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 6BIT 28PLCC 集成电路（IC） 计数器，除法器

封装/外壳：28-LCC（J 形引线） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 6BIT 28PLCC 集成电路（IC） 触发器

5V ECL 6-Bit D Register

文件：127.84 Kbytes Page：8 Pages

5V ECL 6-Bit D Register

文件：127.84 Kbytes Page：8 Pages

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for

6-BIT D REGISTER

DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for