6-BIT D LATCH

Description The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset

5V ECL 6-Bit D Latch

文件：79.56 Kbytes Page：8 Pages

6-BIT D LATCH

5V ECL 6-Bit D Latch

文件：79.56 Kbytes Page：8 Pages

5V ECL 6-Bit D Latch

文件：79.56 Kbytes Page：8 Pages

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC LATCH 6BIT D 5V ECL 28-PLCC 集成电路（IC） 锁存器

5V ECL 6-Bit D Latch

文件：79.56 Kbytes Page：8 Pages

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC LATCH 6BIT D 5V ECL 28-PLCC 集成电路（IC） 锁存器

5V ECL 6-Bit D Latch

文件：79.56 Kbytes Page：8 Pages

6-BIT D LATCH

DESCRIPTION The SY10/100E150 are 6-bit D latches with differential outputs designed for use in new, high- performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output. A logic HIGH on either