位置：首页 > IC中文资料第3563页 > IDT71V3559
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
IDT71V3559 | 3.3V 256K x 18 ZBT Synchronous Flow-Through SRAM w/3.3V I/O | RENESAS 瑞萨 |   | |
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs Description The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | ETC 知名厂家 | ETC | | |
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | ETC 知名厂家 | ETC | | |
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | | ||
Synchronous ZBT SRAMs 文件：298.78 Kbytes Page：28 Pages | IDT | |
IDT71V3559产品属性
- 类型
描述
- 型号
IDT71V3559
- 功能描述
IC SRAM 4MBIT 75NS 119BGA
- RoHS
否
- 类别
集成电路(IC) >> 存储器
- 系列
-
- 标准包装
2,000
- 系列
MoBL® 格式 -
- 存储器
RAM
- 存储器类型
SRAM - 异步
- 存储容量
16M（2M x 8，1M x 16）
- 速度
45ns
- 接口
并联
- 电源电压
2.2 V ~ 3.6 V
- 工作温度
-40°C ~ 85°C
- 封装/外壳
48-VFBGA
- 供应商设备封装
48-VFBGA（6x8）
- 包装
带卷(TR)
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
IDT |
24+ |
NA/ |
3844 |
原装现货,当天可交货,原型号开票 |
|||
IDT |
24+ |
QFP100 |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
IDT |
24+ |
QFP |
20000 |
全新原厂原装，进口正品现货，正规渠道可含税！！ |
|||
IDT |
QFP |
2350 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
IDT |
原厂封装 |
9800 |
原装进口公司现货假一赔百 |
||||
IDT |
24+ |
QFP |
3000 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
IDT |
24+ |
QFP |
7850 |
只做原装正品现货或订货假一赔十! |
|||
idt |
24+ |
N/A |
6980 |
原装现货,可开13%税票 |
|||
IDT |
NEW |
100TQFP |
9526 |
代理全系列销售,全新原装正品,价格优势,长期供应,量大可订 |
|||
IDT |
05+ |
原厂原装 |
4285 |
只做全新原装真实现货供应 |
IDT71V3559芯片相关品牌
IDT71V3559规格书下载地址
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