Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

Dual 4-bit static shift register

1. General description The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (nMR)

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

Dual 4-bit static shift register

1. General description The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (nMR)

Tolerant of slow clock rise and fall times

Tolerant of slow clock rise and fall times

Tolerant of slow clock rise and fall times

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：串行至并行 包装：管件 描述：IC REGISTER STATIC 4BIT 16-SOIC 集成电路（IC） 移位寄存器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：串行至并行 包装：管件 描述：IC STATIC SHIFT REG 4BIT 16SOIC 集成电路（IC） 移位寄存器

Tolerant of slow clock rise and fall times

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Description CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages

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Dual 4-Bit Static Shift Register

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Dual 4-Bit Static Shift Register

CMOS Dual 4-Stage Static Shift Register

CMOS Dual 4-Stage Static Shift Register

Dual 4-bit Static Shift Register

Dual 4-Bit Static Shift Register

Dual 4-Bit Static Shift Register

4−Bit Full Adder

COMPLEMENTARY METAL OXIDE SILICON

Dual 4-Stage Static Shift Register(with serial input/parallel output)

DUAL 4-STAGE STATIC SHIFT REGISTER (WITH SERIAL INPUT/PARALLEL OUTPUT)