Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Description CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages

EPDM Snap-In Liquid Tight Bushings

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EPDM Snap-In Liquid Tight Bushings

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EC Directives Models)

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compact and economical surface-acoustic wave ( SAW ) filter

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4-Bit Latched/4-to-16 Line Decoders

4-Bit Latched/4-to-16 Line Decoders

4-Bit Latched/4-to-16 Line Decoders

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

4-Bit Latched/4-to-16 Line Decoders

Dual 4-bit static shift register

1-of-16 decoder/demultiplexer with input latches

4-Bit Transparent Latch/4-to-16 Line Decoder

4−Bit Transparent Latch / 4−to−16 Line Decoder

4-Bit Transparent Latch/4-to-16 Line Decoder

4-Bit Transparent Latch/4-to-16 Line Decoder

4−Bit Transparent Latch / 4−to−16 Line Decoder

CMOS 4-TO-16 LINE DECODERS WITH LATCH

CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC