位置：首页 > IC中文资料 > HD74LS112P
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
HD74LS112P | Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear) Features • Ordering Information | RENESAS 瑞萨 |   | |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | Motorola 摩托罗拉 | | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | Fairchild 仙童半导体 | | ||
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) ● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....) | HitachiHitachi Semiconductor 日立日立公司 | | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | Fairchild 仙童半导体 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | Motorola 摩托罗拉 | Motorola | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | Fairchild 仙童半导体 | Fairchild | | |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | Fairchild 仙童半导体 | Fairchild | | |
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS | NSC 国半 | NSC | | |
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
Ouadruple 2-input Positive NAND Gates | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
HITACHI |
23+24 |
DIP16 |
28950 |
原装现货.优势热卖.终端BOM表可配单 |
|||
RENESAS |
22+ |
DIP16 |
8000 |
原装正品支持实单 |
|||
RENESAS/瑞萨 |
2023+ |
DIP16 |
15175 |
专注全新正品,优势现货供应 |
|||
Renesas(瑞萨) |
24+ |
标准封装 |
7498 |
支持大陆交货,美金交易。原装现货库存。 |
|||
HIT |
22+ |
PDIP-16 |
20000 |
公司只做原装 品质保障 |
|||
HIT |
DIP |
25635 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
HIT |
24+ |
SOP-14/5.2mm/2 |
37500 |
原装正品现货,价格有优势! |
|||
HIT |
23+ |
DIP |
58942 |
##公司主营品牌长期供应100%原装现货可含税提供技术 |
|||
HIT |
25+ |
DIP-16 |
3200 |
全新原装、诚信经营、公司现货销售 |
|||
RENESAS/瑞萨 |
24+ |
DIP |
20000 |
只做正品原装现货 |
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2019-8-24
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