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74LS112价格
参考价格：￥2.8327
型号：74LS112A 品牌：Semiconductors 备注：这里有74LS112多少钱，2026年最近7天走势，今日出价，今日竞价，74LS112批发/采购报价，74LS112行情走势销售排行榜，74LS112报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74LS112 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | Fairchild 仙童半导体 |   | |
74LS112 | Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) ● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....) | HitachiHitachi Semiconductor 日立日立公司 | | |
74LS112 | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | Motorola 摩托罗拉 | | |
74LS112 | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | |
74LS112 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | ONSEMI 安森美半导体 | | |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | Fairchild 仙童半导体 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP 文件：147.21 Kbytes Page：4 Pages | Motorola 摩托罗拉 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | Fairchild 仙童半导体 | Fairchild | | |
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS | NSC 国半 | NSC | | |
Ouadruple 2-input Positive NAND Gates | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | |
74LS112产品属性
- 类型
描述
- 型号
74LS112
- 制造商
MOTOROLA
- 制造商全称
Motorola, Inc
- 功能描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI/德州仪器 |
24+ |
DIP |
990000 |
明嘉莱只做原装正品现货 |
|||
SIGNETICS |
23+ |
DIP-16 |
9856 |
原装正品,假一罚百! |
|||
TI |
25+23+ |
SOIC-16 |
10412 |
绝对原装正品全新进口深圳现货 |
|||
HIT |
25+ |
DIP |
4500 |
全新原装、诚信经营、公司现货销售 |
|||
74LS112PC |
25+ |
3 |
3 |
||||
TI |
SOP |
650 |
正品原装--自家现货-实单可谈 |
||||
TI |
22+ |
SOIC-16 |
1000 |
全新原装现货!自家库存! |
|||
FAIRCHILD |
新 |
60 |
全新原装 货期两周 |
||||
24+ |
5000 |
公司存货 |
|||||
TI |
23+ |
NA |
20000 |
74LS112规格书下载地址
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2020-9-19
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