| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
HD74LS112 | Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear) Features • Ordering Information | RENESAS 瑞萨 |   | |
HD74LS112 | Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) ● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....) | HITACHIHitachi Semiconductor 日立日立公司 | | |
HD74LS112 | Ouadruple 2-input Positive NAND Gates 文件：6.85482 Mbytes Page：273 Pages | HITACHIHitachi Semiconductor 日立日立公司 | | |
HD74LS112 | Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HITACHIHitachi Semiconductor 日立日立公司 | | |
Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear) Features • Ordering Information | RENESAS 瑞萨 | | ||
Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear) Features • Ordering Information | RENESAS 瑞萨 | | ||
Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear) Features • Ordering Information | RENESAS 瑞萨 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | MOTOROLA 摩托罗拉 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | MOTOROLA 摩托罗拉 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | MOTOROLA 摩托罗拉 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | MOTOROLA 摩托罗拉 | MOTOROLA | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | | |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | FAIRCHILD 仙童半导体 | FAIRCHILD | | |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | FAIRCHILD 仙童半导体 | FAIRCHILD | | |
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS | NSC 国半 | NSC | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
HITACHI/日立 |
15+ |
DIP-16 |
880000 |
明嘉莱只做原装正品现货 |
|||
RENESAS |
22+ |
DIP16 |
8000 |
原装正品支持实单 |
|||
HIT |
25+ |
DIP-16 |
3200 |
全新原装、诚信经营、公司现货销售 |
|||
24+ |
DIP |
1500 |
|||||
HD74LS112P |
25+ |
30 |
30 |
||||
RENESAS/瑞萨 |
2023+ |
DIP16 |
15175 |
专注全新正品,优势现货供应 |
|||
HD |
23+ |
SOP5.2 |
5000 |
原装正品,假一罚十 |
|||
HIT |
26+ |
FBGA84 |
890000 |
一级总代理商原厂原装大批量现货
一站式服务 |
|||
HITACHI/日立 |
24+ |
CDIP |
9600 |
原装现货,优势供应,支持实单! |
|||
RENESAS |
18+ |
DIP |
85600 |
保证进口原装可开17%增值税发票 |
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