型号 功能描述 生产厂家&企业 LOGO 操作
HD74LS112

Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear)

● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....)

HitachiHitachi Semiconductor

日立日立公司

HD74LS112

Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear)

Features • Ordering Information

RENESAS

瑞萨

HD74LS112

Ouadruple 2-input Positive NAND Gates

文件:6.85482 Mbytes Page:273 Pages

HitachiHitachi Semiconductor

日立日立公司

Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear)

Features • Ordering Information

RENESAS

瑞萨

Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear)

Features • Ordering Information

RENESAS

瑞萨

Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear)

Features • Ordering Information

RENESAS

瑞萨

Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear)

● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....)

HitachiHitachi Semiconductor

日立日立公司

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the

Motorola

摩托罗拉

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

文件:300.4 Kbytes Page:9 Pages

TI

德州仪器

替换型号 功能描述 生产厂家&企业 LOGO 操作

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Motorola

摩托罗拉

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

TI

德州仪器

Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear)

HitachiHitachi Semiconductor

日立日立公司

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

TI

德州仪器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR

TI

德州仪器

更新时间:2025-8-12 20:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
Renesas(瑞萨)
24+
NA/
8735
原厂直销,现货供应,账期支持!
HITACHI
11+
DIP
1200
一级代理,专注军工、汽车、医疗、工业、新能源、电力
HD74LS112P
30
30
HIT
25+
DIP-16
3200
全新原装、诚信经营、公司现货销售
HIT
DIP
25635
一级代理 原装正品假一罚十价格优势长期供货
HITACHI/日立
15+
DIP-16
880000
明嘉莱只做原装正品现货
RENESAS
2024+
N/A
70000
柒号只做原装 现货价秒杀全网
HIT
2016+
CDIP
3900
只做原装,假一罚十,公司可开17%增值税发票!
RENESAS
22+
DIP16
8000
原装正品支持实单
HITACHI/日立
2223+
CDIP
26800
只做原装正品假一赔十为客户做到零风险

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