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SN74LS112AD价格
参考价格：￥1.9428
型号：SN74LS112AD 品牌：TI 备注：这里有SN74LS112AD多少钱，2025年最近7天走势，今日出价，今日竞价，SN74LS112AD批发/采购报价，SN74LS112AD行情走势销售排行榜，SN74LS112AD报价。| 型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
|---|---|---|---|---|
SN74LS112AD | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 |   | |
SN74LS112AD | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件：697.41 Kbytes Page：17 Pages | TI 德州仪器 | | |
SN74LS112AD | DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件：1.32368 Mbytes Page：20 Pages | TI1 德州仪器 | | |
SN74LS112AD | 封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | TI2 德州仪器 | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件：697.41 Kbytes Page：17 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件：697.41 Kbytes Page：17 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件：1.32368 Mbytes Page：20 Pages | TI1 德州仪器 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路（IC） 触发器 | TI2 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件：697.41 Kbytes Page：17 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件：1.32368 Mbytes Page：20 Pages | TI1 德州仪器 | | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) ● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....) | HitachiHitachi Semiconductor 日立日立公司 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | Motorola 摩托罗拉 | | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | |
SN74LS112AD产品属性
- 类型
描述
- 型号
SN74LS112AD
- 功能描述
触发器 Dual Neg-Edge-Trig J-K Flip-Flop
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
SOP |
4500 |
全新原装、诚信经营、公司现货销售! |
|||
TI |
2016+ |
SOP16 |
6528 |
只做进口原装现货!假一赔十! |
|||
FSC |
25+23+ |
SOP16 |
54389 |
绝对原装正品现货,全新深圳原装进口现货 |
|||
TI/德州仪器 |
23+ |
SOP16 |
11200 |
原厂授权一级代理、全球订货优势渠道、可提供一站式BO |
|||
TI |
22+ |
16SOIC |
9000 |
原厂渠道,现货配单 |
|||
Texas Instruments |
23+ |
16-SOIC |
3500 |
只做原装,假一赔十 |
|||
TI |
2025+ |
SOIC-16 |
16000 |
原装优势绝对有货 |
|||
24+ |
3000 |
自己现货 |
|||||
TI |
23+ |
SOIC |
3200 |
正规渠道,只有原装! |
|||
TI |
2021 |
BGA |
1000 |
全新、原装 |
SN74LS112AD规格书下载地址
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SN74LS112AD数据表相关新闻
SN74LS125ADR
SN74LS125ADR
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SN74LS123DRG4
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原装正品，价格优势，竭力为您服务 0755-88600196/QQ3007281353
2019-6-24
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