SN74LS112A价格
参考价格:¥1.9428
型号:SN74LS112AD 品牌:TI 备注:这里有SN74LS112A多少钱,2026年最近7天走势,今日出价,今日竞价,SN74LS112A批发/采购报价,SN74LS112A行情走势销售排行榜,SN74LS112A报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SN74LS112A | 具有清零和预置端的双路负边沿触发式 J-K 触发器 These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements • Fully Buffered to Offer Maximum Isolation from External Disturbance\n• Package Options Include Plastic “Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability; | TI 德州仪器 | ||
SN74LS112A | DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI 德州仪器 | ||
SN74LS112A | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件:300.4 Kbytes Page:9 Pages | TI 德州仪器 | ||
SN74LS112A | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件:300.4 Kbytes Page:9 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI 德州仪器 | |||
封装/外壳:16-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:卷带(TR) 描述:IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路(IC) 触发器 | TI 德州仪器 | |||
封装/外壳:16-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:卷带(TR) 描述:IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路(IC) 触发器 | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件:300.4 Kbytes Page:9 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | |||
74系列逻辑芯片 | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件:1.32368 Mbytes Page:20 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | |||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件:697.41 Kbytes Page:17 Pages | TI 德州仪器 | |||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | MOTOROLA 摩托罗拉 | |||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | MOTOROLA 摩托罗拉 | |||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | MOTOROLA 摩托罗拉 |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | MOTOROLA 摩托罗拉 | MOTOROLA | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | FAIRCHILD 仙童半导体 | FAIRCHILD | ||
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | ||
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS | NSC 国半 | NSC | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | FAIRCHILD 仙童半导体 | FAIRCHILD | ||
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI | ||
Ouadruple 2-input Positive NAND Gates | HITACHIHitachi Semiconductor 日立日立公司 | HITACHI |
SN74LS112A产品属性
- 类型
描述
- Technology Family:
LS
- Supply voltage (Min) (V):
4.75
- Supply voltage (Max) (V):
5.25
- Input type:
TTL
- Output type:
Push-Pull
- Clock Frequency (MHz):
30
- ICC (Max) (uA):
6000
- IOL (Max) (mA):
8
- IOH (Max) (mA):
-0.4
- Features:
Negative edge triggered
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
23+ |
DIP |
5000 |
原装正品,假一罚十 |
|||
TI |
25+ |
- |
18798 |
原装正品现货,原厂订货,可支持含税原型号开票。 |
|||
TI |
23+ |
SOP5.2 |
5000 |
全新原装,支持实单,非诚勿扰 |
|||
最新 |
2000 |
原装正品现货 |
|||||
Texas Instruments |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
TI/德州仪器 |
DIP-16 |
6000 |
只做原装正品,卖元器件不赚钱交个朋友 |
||||
TI |
92+ |
DIP-16 |
18 |
原装现货海量库存欢迎咨询 |
|||
TI/德州仪器 |
2020+ |
DIP-16 |
7600 |
||||
TI |
24+ |
con |
10000 |
查现货到京北通宇商城 |
|||
TI |
24+ |
DIP |
825 |
新 |
SN74LS112A规格书下载地址
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原装正品,价格优势,竭力为您服务 0755-88600196/QQ3007281353
2019-6-24
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