10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path

General Description The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing ( F

10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path

General Description The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing ( F

CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

General Description The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane o

CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

General Description The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane o

CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

General Description The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane o

17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

General Description The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed in

17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

General Description The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed in

17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

General Description The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed in

17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock

General Description The GTLP16617 is a 17-bit registered synchronous bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a h

17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock

General Description The GTLP16617 is a 17-bit registered synchronous bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a h

17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock

General Description The GTLP16617 is a 17-bit registered synchronous bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a h

16-Bit LVTTL/GTLP Universal Bus Transceiver

General Description The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a bac

16-Bit LVTTL/GTLP Universal Bus Transceiver

General Description The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a bac

17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock

General Description The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB. The device provides a high spe

17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock

General Description The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB. The device provides a high spe

17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock

General Description The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB. The device provides a high spe

18-Bit LVTTL/GTLP Universal Bus Transceiver

General Description The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backpl

18-Bit LVTTL/GTLP Universal Bus Transceiver

General Description The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backpl

18-Bit LVTTL/GTLP Universal Bus Transceiver

General Description The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backpl

1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path

General Description The GTLP1B151 is a 1-bit transceiver that provides LVTTL-to-GTLP signal level translation. Individual LVTTL and GTLP driver enables are also available. The GTLP1B151 offers separate LVTTL inputs and outputs, and can provide a feedback path for control and diagnostics monitorin

1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path

General Description The GTLP1B151 is a 1-bit transceiver that provides LVTTL-to-GTLP signal level translation. Individual LVTTL and GTLP driver enables are also available. The GTLP1B151 offers separate LVTTL inputs and outputs, and can provide a feedback path for control and diagnostics monitorin

1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path

General Description The GTLP1B151 is a 1-bit transceiver that provides LVTTL-to-GTLP signal level translation. Individual LVTTL and GTLP driver enables are also available. The GTLP1B151 offers separate LVTTL inputs and outputs, and can provide a feedback path for control and diagnostics monitorin

1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path

General Description The GTLP1B151 is a 1-bit transceiver that provides LVTTL-to-GTLP signal level translation. Individual LVTTL and GTLP driver enables are also available. The GTLP1B151 offers separate LVTTL inputs and outputs, and can provide a feedback path for control and diagnostics monitorin

36-Bit LVTTL/GTLP Universal Bus Transceiver

General Description The GTLP36T612 is an 36-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backpl

36-Bit LVTTL/GTLP Universal Bus Transceiver

General Description The GTLP36T612 is an 36-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backpl

GTLP-to-TTL 1:6 Clock Driver

General Description The GTLP6C816 is a clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direc

LVTTL-to-GTLP Clock Driver

General Description The GTLP6C816A is a clock driver that provides LVTTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL(P) logic levels. High speed backplane operation is

LVTTL-to-GTLP Clock Driver

General Description The GTLP6C816A is a clock driver that provides LVTTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL(P) logic levels. High speed backplane operation is

GTLP-to-TTL 1:6 Clock Driver

General Description The GTLP6C816 is a clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direc

Low Drive GTLP-to-LVTTL 1:6 Clock Driver

General Description The GTLP6C817 is a low drive clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation

Low Drive GTLP-to-LVTTL 1:6 Clock Driver

General Description The GTLP6C817 is a low drive clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation

8-Bit LVTTL/GTLP Bus Transceiver

General Description The GTLP8T306 is an 8-bit bus transceiver that provides LVTTL to GTLP signal level translation. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct r

8-Bit LVTTL/GTLP Bus Transceiver

General Description The GTLP8T306 is an 8-bit bus transceiver that provides LVTTL to GTLP signal level translation. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct r

封装/外壳：56-TFSOP（0.240"，6.10mm 宽） 包装：管件 描述：IC UNIV BUS DVR 10BIT 56TSSOP 集成电路（IC） 通用总线功能

CMOS 18-Bit TTL/GTLP Universal Bus Transceiver

CMOS 18-bit TTL/GTLP universal bus transceiver

封装/外壳：56-BSSOP（0.295"，7.50mm 宽） 包装：管件 描述：IC UNIV BUS TXRX 18BIT 56SSOP 集成电路（IC） 通用总线功能

17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

文件：435.12 Kbytes Page：21 Pages

2-Bit LVTTL/GTLP Transceiver

文件：114.14 Kbytes Page：7 Pages

2-Bit LVTTL/GTLP Transceiver

文件：114.14 Kbytes Page：7 Pages

2-Bit LVTTL/GTLP Transceiver

文件：114.14 Kbytes Page：7 Pages

2-Bit LVTTL/GTLP Transceiver

文件：114.14 Kbytes Page：7 Pages

18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER

文件：157.59 Kbytes Page：15 Pages

18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS

文件：361.48 Kbytes Page：19 Pages