General Description

The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus set tling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.

Features

■ Bidirectional interface between GTLP and LVTTL logic levels

■ Variable edge rate control pin to select desired edge rate

on the GTLP backplane (VERC)

■ VREF pin provides external supply reference voltage for

receiver threshold adjustibility

■ Special PVT compensation circuitry to provide consis

tent performance over variations of process, supply volt

age and temperature

■ TTL compatible driver and control inputs

■ Designed using Fairchild advanced BiCMOS technology

■ Bushold data inputs on A port to eliminate the need for

external pull-up resistors for unused inputs

■ Power up/down and power off high impedance for live insertion

■ Open drain on GTLP to support wired-or connection

■ Flow through pinout optimizes PCB layout

■ D-type flip-flop, latch and transparent data paths

■ A Port source/sink −24mA/+24mA

■ B Port sink +100mA

■ Partitioned as two 8-bit transceivers with individual latch

timing and output control but with a common clock

■ External pin to pre-condition I/O capacitance to high

state (VCCBIAS)