General Description

The GTLP16617 is a 17-bit registered synchronous bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels.

High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input thresh old levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.

Features

■ Bidirectional interface between GTLP and TTL logic levels

■ Designed with edge rate control circuitry to reduce output noise on the GTLP port

■ VREF pin provides external supply reference voltage for receiver threshold adjustibility

■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature

■ TTL compatible driver and control inputs

■ Designed using Fairchild advanced CMOS technology

■ Bushold data inputs on the A port eliminates the need for external pull-up resistors on unused inputs.

■ Power up/down and power off high impedance for live insertion

■ 5 V tolerant inputs and outputs on the LVTTL port

■ Open drain on GTLP to support wired-or connection

■ Flow through pinout optimizes PCB layout

■ D-type flip-flop, latch and transparent data paths

■ A Port source/sink −32 mA/+32 mA

■ GTLP Buffered CLKAB signal available (CLKOUT)