General Description

The GTLP8T306 is an 8-bit bus transceiver that provides LVTTL to GTLP signal level translation. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3.

Features

■ Bidirectional interface between GTL/GTLP and LVTTL

logic levels

■ Output Edge Rate Control to minimize noise on the

GTLP port

■ Power up/down/off high impedance for live insertion

■ Standard 245 function

■ CMOS technology for low power dissipation

■ 5V tolerant inputs and outputs on the A-Port

■ Bus-hold data inputs on the A-Port eliminates the need

for external pull-up resistors on unused inputs

■ LVTTL compatible driver and control inputs

■ Flow through pinout optimizes PCB layout

■ Open drain on GTLP to support wired-or connection

■ A-Port source/sink −24 mA/+24 mA

■ B-Port sink 50 mA

■ Recommended Operating Temperature −40°C to +85°C