GAL22V10D价格

参考价格:¥75.7917

型号:GAL22V10D-25LPI 品牌:Lattice Semi 备注:这里有GAL22V10D多少钱,2025年最近7天走势,今日出价,今日竞价,GAL22V10D批发/采购报价,GAL22V10D行情走势销售排行榜,GAL22V10D报价。
型号 功能描述 生产厂家 企业 LOGO 操作
GAL22V10D

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much l

Lattice

莱迪思

GAL 22V10 Device Datasheet

Description The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much les

Lattice

莱迪思

GAL22V10D产品属性

  • 类型

    描述

  • 型号

    GAL22V10D

  • 功能描述

    Electrically-Erasable PLD

更新时间:2025-12-29 8:40:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
LATTICE
24+
PLCC28
8100
绝对原装现货,价格低,欢迎询购!
LATTICE/莱迪斯
23+
PLCC
98900
原厂原装正品现货!!
LATTICE
17+
DIP
6200
100%原装正品现货
LATTICE
2016+
PLCC28
4530
只做原装,假一罚十,公司可开17%增值税发票!
LATTICE
24+
DIP24
9860
一级代理/全新现货/长期供应!
LATTICE/莱迪斯
24+
DIP24
8000
只做原装正品现货
Lattice(莱迪斯)
24+
标准封装
7818
原厂渠道供应,大量现货,原型号开票。
LATTICE/莱迪斯
25+23+
PLCC28
13397
绝对原装正品全新进口深圳现货
Lattice(莱迪斯)
24+
24-DIP(0.300
7848
LATTICE/莱迪斯
21+
DIP24
9080
只做原装,质量保证

GAL22V10D芯片相关品牌

GAL22V10D数据表相关新闻