位置：首页 > IC中文资料第927页 > DM74LS112A
| 型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
|---|---|---|---|---|
DM74LS112A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 |   | |
DM74LS112A | DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS 文件：102.78 Kbytes Page：3 Pages | NSCNational Semiconductor (TI) 美国国家半导体美国国家半导体公司 | | |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS 文件：102.78 Kbytes Page：3 Pages | NSCNational Semiconductor (TI) 美国国家半导体美国国家半导体公司 | | ||
DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS 文件：102.78 Kbytes Page：3 Pages | NSCNational Semiconductor (TI) 美国国家半导体美国国家半导体公司 | | ||
封装/外壳：16-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16DIP 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) ● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....) | HitachiHitachi Semiconductor 日立日立公司 | | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | Motorola 摩托罗拉 | | ||
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | |
| 替换型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
|---|---|---|---|---|
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | Motorola 摩托罗拉 | Motorola | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | | |
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
Ouadruple 2-input Positive NAND Gates | HitachiHitachi Semiconductor 日立日立公司 | Hitachi | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | TI 德州仪器 | TI | | |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | TI 德州仪器 | TI | |
DM74LS112A产品属性
- 类型
描述
- 型号
DM74LS112A
- 制造商
Fairchild Semiconductor Corporation
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
24+ |
N/A |
80000 |
一级代理-主营优势-实惠价格-不悔选择 |
||||
NS/国半 |
2447 |
DIP16 |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
|||
TI/德州仪器 |
23+ |
DIP16 |
50000 |
全新原装正品现货,支持订货 |
|||
NS |
24+ |
DIP16 |
250 |
||||
FAI |
23+ |
DIP |
7000 |
绝对全新原装!100%保质量特价!请放心订购! |
|||
Rochester |
25+ |
电联咨询 |
7800 |
公司现货,提供拆样技术支持 |
|||
Fairchild/ON |
22+ |
16DIP |
9000 |
原厂渠道,现货配单 |
|||
FAIRCILD |
22+ |
DIP-16 |
8000 |
原装正品支持实单 |
|||
ON Semiconductor |
24+ |
16-DIP(0.300 |
56300 |
||||
FAI |
DIP16 |
6500 |
一级代理 原装正品假一罚十价格优势长期供货 |
DM74LS112A芯片相关品牌
DM74LS112A规格书下载地址
DM74LS112A参数引脚图相关
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DM74LS112A数据表相关新闻
DM54S574J/883C
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2020-7-10DM74LS241WM，DM74LS241WMX，DM74LS243N，DM74LS244N，DM74LS244SJX，DM74LS245N，DM74LS245SJX，DM74LS251M，DM74LS251MX，DM74LS251N，DM74LS253MX，DM74LS257BMX，DM74LS221MX，DM74LS221SJ，DM74LS221
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DM74AS169AN，P6KE200AT/B，UEP1H220MPD1TD，DM9328N，1N5232B(T50A)，LS3360L，LT1E53A，MC14511BDWR2，SMA020450100R1%A2，SAA1064T，DM74AS257M
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2012-11-9
DdatasheetPDF页码索引
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