144-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1613KV18, and CY7C1615KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR® II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support

144-Mbit QDR짰 II SRAM Two-Word Burst Architecture

Functional Description The CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outpu

144-Mbit QDR짰 II SRAM Four-Word Burst Architecture

Functional Description The CY7C1613KV18, and CY7C1615KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR® II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support

144-Mbit DDR II SRAM Two-Word Burst Architecture

Functional Description The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate ris

144-Mbit DDR II SRAM Two-Word Burst Architecture

Functional Description The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate ris

144-Mbit DDR II SRAM Two-Word Burst Architecture

Functional Description The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate ris

同步 SRAM

Synchronous SRAM

封装/外壳：165-LBGA 包装：管件 描述：IC SRAM 144MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 144MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

同步 SRAM

144-Mbit DDR II SRAM Two-Word Burst Architecture

文件：1.22023 Mbytes Page：32 Pages

144-Mbit DDR II SRAM Two-Word Burst Architecture

文件：1.22023 Mbytes Page：32 Pages

144-Mbit DDR II SRAM Two-Word Burst Architecture

文件：1.22023 Mbytes Page：32 Pages