CY7C146价格

参考价格:¥312.0016

型号:CY7C1460AV25-167AXC 品牌:Cynergy 3 备注:这里有CY7C146多少钱,2025年最近7天走势,今日出价,今日竞价,CY7C146批发/采购报价,CY7C146行情走势销售排行榜,CY7C146报价。
型号 功能描述 生产厂家&企业 LOGO 操作
CY7C146

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

CY7C146

2K x 8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

CY7C146

2K x 8 Dual-Port Static RAM

文件:562.22 Kbytes Page:18 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

CY7C146

2K x 8 Dual-Port Static RAM High speed access: 15 ns

文件:443.27 Kbytes Page:15 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

2Kx8 Dual-Port Static RAM

Functional Description The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146 are high speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136, and CY7C136A can be used as either a standalone 8-bit dual-port static

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

CY7C146产品属性

  • 类型

    描述

  • 型号

    CY7C146

  • 功能描述

    静态随机存取存储器 1Mx36 2.5V NoBL PL 静态随机存取存储器 COM

  • RoHS

  • 制造商

    Cypress Semiconductor

  • 存储容量

    16 Mbit

  • 组织

    1 M x 16

  • 访问时间

    55 ns

  • 电源电压-最大

    3.6 V

  • 电源电压-最小

    2.2 V

  • 最大工作电流

    22 uA

  • 最大工作温度

    + 85 C

  • 最小工作温度

    - 40 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    TSOP-48

  • 封装

    Tray

更新时间:2025-8-7 19:45:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
CYPRESS/赛普拉斯
25+
QFP100
12496
CYPRESS/赛普拉斯原装正品CY7C1462AV33-167AXC即刻询购立享优惠#长期有货
CYPRESS
24+
100TQFP
4568
全新原厂原装,进口正品现货,正规渠道可含税!!
Cypress
24+
TQFP100
8540
只做原装正品现货或订货假一赔十!
CYPRESS
23+
QFP
20000
原装进口ICMCUSOCMOS等知名国内外品牌只做原装全
CYPRESS
2138+
QFP
8960
专营BGA,QFP原装现货,假一赔十
Cypress
23+
100-TQFP
65600
CYPRESS
24+
PLCC
5650
公司原厂原装现货假一罚十!特价出售!强势库存!
CYPRESS
23+
LQFP-100
730
只做原装全系列供应价格优势
CYPRESS
24+
TQFP-100
2
低于市场价,实单必成,QQ1562321770
CYPRESS
24+
BGA
23000
免费送样原盒原包现货一手渠道联系

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