CD74HCT10价格

参考价格:¥1.3224

型号:CD74HCT107E 品牌:TI 备注:这里有CD74HCT10多少钱,2025年最近7天走势,今日出价,今日竞价,CD74HCT10批发/采购报价,CD74HCT10行情走势销售排行榜,CD74HCT10报价。
型号 功能描述 生产厂家 企业 LOGO 操作
CD74HCT10

CDx4HCT10 Triple 3-Input NAND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

TI

德州仪器

CD74HCT10

具有 TTL 兼容型 CMOS 输入的 3 通道、3 输入、4.5V 至 5.5V 与非门

TI

德州仪器

CD74HCT10

High Speed CMOS Logic Triple 3-Input NAND Gate

文件:41.15 Kbytes Page:6 Pages

TI

德州仪器

CD74HCT10

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件:265.51 Kbytes Page:10 Pages

TI

德州仪器

CD74HCT10

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件:261.209 Kbytes Page:11 Pages

TI

德州仪器

CD74HCT10

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件:32.159 Kbytes Page:5 Pages

TI

德州仪器

CD74HCT10

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件:614.15 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi

TI

德州仪器

CDx4HCT10 Triple 3-Input NAND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

TI

德州仪器

CDx4HCT10 Triple 3-Input NAND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

TI

德州仪器

CDx4HCT10 Triple 3-Input NAND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

TI

德州仪器

CDx4HCT10 Triple 3-Input NAND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

TI

德州仪器

CDx4HCT10 Triple 3-Input NAND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

TI

德州仪器

CDx4HCT10 Triple 3-Input NAND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

TI

德州仪器

CDx4HCT10 Triple 3-Input NAND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

TI

德州仪器

具有复位功能的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件:624.14 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件:451.69 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件:56.86 Kbytes Page:8 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件:56.86 Kbytes Page:8 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件:266.26 Kbytes Page:11 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件:451.69 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件:624.14 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件:624.14 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件:451.69 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:58.14 Kbytes Page:8 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:454.62 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:279.59 Kbytes Page:12 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:347.95 Kbytes Page:16 Pages

TI

德州仪器

具有设置和复位端的高速 CMOS 逻辑双路正边沿触发式 J-K 触发器

TI

德州仪器

封装/外壳:16-DIP(0.300",7.62mm) 功能:设置(预设)和复位 包装:管件 描述:IC FF JK TYPE DUAL 1BIT 16DIP 集成电路(IC) 触发器

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:279.59 Kbytes Page:12 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:347.95 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:454.62 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:454.62 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:347.95 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:347.95 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:279.59 Kbytes Page:12 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:454.62 Kbytes Page:15 Pages

TI

德州仪器

封装/外壳:16-SOIC(0.154",3.90mm 宽) 功能:设置(预设)和复位 包装:管件 描述:IC FF JK TYPE DUAL 1BIT 16SOIC 集成电路(IC) 触发器

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:454.62 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:347.95 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:279.59 Kbytes Page:12 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:347.95 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:454.62 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:454.62 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:347.95 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:347.95 Kbytes Page:16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:454.62 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:454.62 Kbytes Page:15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

文件:347.95 Kbytes Page:16 Pages

TI

德州仪器

CD74HCT10产品属性

  • 类型

    描述

  • 型号

    CD74HCT10

  • 功能描述

    触发器 Hi-Spd CMOS Dual Neg J-K Flip-Flop

  • RoHS

  • 制造商

    Texas Instruments

  • 电路数量

    2

  • 逻辑系列

    SN74

  • 逻辑类型

    D-Type Flip-Flop

  • 极性

    Inverting, Non-Inverting

  • 输入类型

    CMOS

  • 传播延迟时间

    4.4 ns

  • 高电平输出电流

    - 16 mA

  • 低电平输出电流

    16 mA

  • 电源电压-最大

    5.5 V

  • 最大工作温度

    + 85 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    X2SON-8

  • 封装

    Reel

更新时间:2025-12-25 23:01:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
TI(德州仪器)
24+
SOP14
2669
只做原装,提供一站式配单服务,代工代料。BOM配单
HAR
23+
NA
20000
全新原装假一赔十
TI
23+
NA
20000
HAR
24+
DIP-14
37500
原装正品现货,价格有优势!
TI
23+
14-SOIC
65600
HAR
21+
DIP
1398
只做原装正品,不止网上数量,欢迎电话微信查询!
TI
25+
SOP-14
2250
百分百原装正品 真实公司现货库存 本公司只做原装 可
TI/德州仪器
22+
SOIC-14_150mil
500000
原装现货支持实单价优/含税
Harris
25+
6
公司优势库存 热卖中!!
TI/德州仪器
20+
NA
53650
TI原装主营-可开原型号增税票

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