N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR

Description • N-channel enhancement mode field effect transistor, designed for high speed pulsed amplifier and driver applications, which is manufactored by the N-Channel DMOS process. Features • High density cell design for low RDS(ON). • Voltage controlled small signal switching. • Rugged a

N-Channel Enhancement-Mode Vertical DMOS FETs

General Description The Supertex 2N7002 is an enhancement-mode (normally off) transistor that utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors, and the h

N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

FEATURES * 60 Volt VCEO

N-Channel 60-V (D-S) MOSFET

FEATURES ● Low On-Resistance: 2.5 Ω ● Low Threshold: 2.1 V ● Low Input Capacitance: 22 pF ● Fast Switching Speed: 7 ns ● Low Input and Output Leakage BENEFITS ● Low Offset Voltage ● Low-Voltage Operation ● Easily Driven Without Buffer ● High-Speed Circuits ● Low Error Voltage APPLICATI

N-Channel Enhancement Mode Field Effect Transistor

Description These N-channel enhancement mode field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. These products have been designed to minimize on-state resistance while providing rugged, reliable, and fast switching performance. They can be used

N-Channel 60-V (D-S) MOSFET

DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the

N-Channel 60-V (D-S) MOSFET

DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the

N-Channel 60-V (D-S) MOSFET

DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the

N-Channel 60-V (D-S) MOSFET

DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the

Evaluating the LTC2688 16-Channel, 16-Bit Voltage Output SoftSpan DAC

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