SN54LS11价格
参考价格：￥57.2638
型号：SN54LS112AJ 品牌：TI 备注：这里有SN54LS11多少钱，2026年最近7天走势，今日出价，今日竞价，SN54LS11批发/采购报价，SN54LS11行情走势销售排行榜，SN54LS11报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SN54LS11 | TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE LOW POWER SCHOTTKY | MOTOROLA 摩托罗拉 |   | |
SN54LS11 | 军用 3 通道、3 输入、4.5V 至 5.5V 双极与门 These devices contain three independent 3-input AND gates. The SN54LS11 and SN54S11 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS11 and SN74S11 are characterized for operation from 0°C to 70°C. • Package Options Include Plastic \"Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability; | TI 德州仪器 | | |
SN54LS11 | TRIPLE 3-INPUT POSITIVE-AND GATES 文件：179.08 Kbytes Page：7 Pages | TI 德州仪器 | | |
SN54LS11 | TRIPLE 3-INPUT POSITIVE-AND GATES 文件：153.88 Kbytes Page：5 Pages | TI 德州仪器 | | |
SN54LS11 | TRIPLE 3-INPUT POSITIVE-AND GATES 文件：1.096 Mbytes Page：17 Pages | TI 德州仪器 | | |
具有预置和清零端的双路负边沿触发式 J-K 触发器 These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements • Fully Buffered to Offer Maximum Isolation from External Disturbance\n• Package Options Include Plastic “Small Outline\" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs\n• Dependable Texas Instruments Quality and Reliability; | TI 德州仪器 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | MOTOROLA 摩托罗拉 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS112A dual JKflip-flop features individual J, K, clock, and asynchronousset and clear inputs to each flip-flop. When the clock goes HIGH,the inputs are enabled and data will be accepted. The logic level of the Jand K inputs may be allowed to change when the clock pulse is HIGH and the | MOTOROLA 摩托罗拉 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha | MOTOROLA 摩托罗拉 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha | MOTOROLA 摩托罗拉 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to cha | MOTOROLA 摩托罗拉 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed sothat when the clock goes HIGH, the inputs are enabled and data will be accepted.The logic level of the J and K inputs may be allowed to change when the | MOTOROLA 摩托罗拉 | | ||
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed sothat when the clock goes HIGH, the inputs are enabled and data will be accepted.The logic level of the J and K inputs may be allowed to change when the | MOTOROLA 摩托罗拉 | | ||
TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE LOW POWER SCHOTTKY | MOTOROLA 摩托罗拉 | | ||
TRIPLE 3-INPUT POSITIVE-AND GATES 文件：1.096 Mbytes Page：17 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件：697.41 Kbytes Page：17 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件：1.32368 Mbytes Page：20 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件：1.32368 Mbytes Page：20 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件：697.41 Kbytes Page：17 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件：697.41 Kbytes Page：17 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS 文件：1.32368 Mbytes Page：20 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR 文件：697.41 Kbytes Page：17 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR 文件：300.4 Kbytes Page：9 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET 文件：259.97 Kbytes Page：6 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET 文件：259.97 Kbytes Page：6 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET 文件：259.97 Kbytes Page：6 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET 文件：259.97 Kbytes Page：6 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK 文件：240.11 Kbytes Page：8 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK 文件：240.11 Kbytes Page：8 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK 文件：240.11 Kbytes Page：8 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK 文件：240.11 Kbytes Page：8 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK 文件：240.11 Kbytes Page：8 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK 文件：240.11 Kbytes Page：8 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK 文件：240.11 Kbytes Page：8 Pages | TI 德州仪器 | | ||
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK 文件：240.11 Kbytes Page：8 Pages | TI 德州仪器 | | ||
TRIPLE 3-INPUT POSITIVE-AND GATES 文件：179.08 Kbytes Page：7 Pages | TI 德州仪器 | | ||
TRIPLE 3-INPUT POSITIVE-AND GATES 文件：153.88 Kbytes Page：5 Pages | TI 德州仪器 | | ||
TRIPLE 3-INPUT POSITIVE-AND GATES 文件：1.096 Mbytes Page：17 Pages | TI 德州仪器 | | ||
TRIPLE 3-INPUT POSITIVE-AND GATES 文件：153.88 Kbytes Page：5 Pages | TI 德州仪器 | | ||
TRIPLE 3-INPUT POSITIVE-AND GATES 文件：179.08 Kbytes Page：7 Pages | TI 德州仪器 | | ||
TRIPLE 3-INPUT POSITIVE-AND GATES 文件：179.08 Kbytes Page：7 Pages | TI 德州仪器 | | ||
TRIPLE 3-INPUT POSITIVE-AND GATES 文件：153.88 Kbytes Page：5 Pages | TI 德州仪器 | | ||
Triple 3-Input AND Gates 文件：120.78 Kbytes Page：6 Pages | NSC 国半 | | ||
Triple 3-Input AND Gates 文件：120.78 Kbytes Page：6 Pages | NSC 国半 | | ||
Triple 3-Input AND Gates 文件：120.78 Kbytes Page：6 Pages | NSC 国半 | |
SN54LS11产品属性
- 类型
描述
- Supply voltage (Min) (V)：
4.5
- Supply voltage (Max) (V)：
5.5
- Number of channels (#)：
3
- Inputs per channel：
3
- IOL (Max) (mA)：
8
- IOH (Max) (mA)：
-0.4
- Input type：
Bipolar
- Output type：
Push-Pull
- Features：
High speed (tpd 10- 50ns)
- Data rate (Max) (Mbps)：
35
- Rating：
Military
- Operating temperature range (C)：
-55 to 125
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
25+23+ |
DIP |
51802 |
绝对原装正品现货,全新深圳原装进口现货 |
|||
TI/TEXAS |
26+ |
DIP陶瓷 |
8931 |
代理全系列销售, 全新原装正品,价格优势,长期供应,量大可订 |
|||
MOTOROLA |
22+ |
CDIP |
3000 |
原装正品,支持实单 |
|||
TI |
25+ |
DIP |
3000 |
全新原装、诚信经营、公司现货销售! |
|||
TI/德州仪器 |
2025+ |
CDIP-14 |
5000 |
原装进口,免费送样品! |
|||
onsemi |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
SN54LS11J |
25+ |
2 |
2 |
||||
TI |
17+ |
DIP |
6200 |
100%原装正品现货 |
|||
TI |
24+ |
n/a |
3000 |
自己现货 |
|||
TI |
23+ |
7/TO220 |
5000 |
原装正品,假一罚十 |
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SN54LS11规格书下载地址
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