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PLL1价格
参考价格：￥25.6860
型号：PLL1700E 品牌：TI 备注：这里有PLL1多少钱，2025年最近7天走势，今日出价，今日竞价，PLL1批发/采购报价，PLL1行情走势销售排行榜，PLL1报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
PLL1 | 30 mm Replacement Lenses for pilot lights PLLx (x=color) 文件：191.17 Kbytes Page：1 Pages | ALTECH |   | |
PLL1 | 包装：散装 描述：LENSPILOT LIGHT 30 MM WHITE 光电器件 配件 | ALTECH | | |
PLL1 | Cyclone III Device Handbook | Intel 英特尔 | | |
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
PHASE LOCKED LOOP [Z-Communications, Inc.] FEATURES • Frequency Range: 988 - 1028 MHz • Step Size: 1000 KHz • PLL - Style Package APPLICATIONS • Basestations • Mobile Radios • Satellite Communications | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Low Skew Output Buffer DESCRIPTIONS The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to t | PLL | | ||
Low Skew Output Buffer DESCRIPTIONS The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to t | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | |
PLL1产品属性
- 类型
描述
- 型号
PLL1
- 功能描述
开关配件 Lens, Pilot Light, 30 mm,White
- RoHS
否
- 制造商
C&K Components
- 类型
Cap
- 用于
Pushbutton Switches
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Phaselink |
0608+ |
SOP8 |
1628 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
23+ |
360000 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
|||||
TI/德州仪器 |
25+ |
SSOP20 |
32000 |
TI/德州仪器全新特价PLL1708DBQR即刻询购立享优惠#长期有货 |
|||
TI德州仪器 |
22+ |
SSOP20 |
2000 |
原装正品现货假一罚十 |
|||
CHINA |
23+ |
连接器 |
3200 |
绝对全新原装!优势供货渠道!特价!请放心订购! |
|||
TI |
2430+ |
SSOP20 |
8540 |
只做原装正品假一赔十为客户做到零风险!! |
|||
TI |
23+ |
PSOP20 |
214 |
新到现货 全新原装 |
|||
TI |
25+ |
29 |
全新原装!优势库存热卖中! |
||||
PHASELINK |
25+ |
TQFP |
18000 |
原厂直接发货进口原装 |
|||
TI |
2025+ |
SOP |
3925 |
全新原装、公司现货热卖 |
PLL1规格书下载地址
PLL1参数引脚图相关
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- PLL2_C4
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- PLL1708DBQ
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- PLL1707DBQG4
- PLL1707DBQ
- PLL1707
- PLL1706DBQG4
- PLL1706DBQ
- PLL1706
- PLL1705DBQR
- PLL1705DBQ
- PLL1705
- PLL1700E
- PLL1700
- PLL-15-Y2-10
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- PLL1_C4
- PLL1_C3
- PLL1_C2
- PLL1_C1
- PLL1_C0
- PLI9080
- PLHS501
- PLH-3R
- PLH-2A
- PLH250P
- PLH250
- PLH-1R
- PLH16
- PLH120P
- PLH120
- PLH10AS7003R6P2B
- PLH10AS3711R0P2B
- PLH10AS2211R5P2B
- PLH10AS1612R1P2B
- PLH10AN7003R6P2B
- PLH10AN3711R0P2B
- PLH10AN2211R5P2B
- PLH10AN1612R1P2B
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- PLG1C821MDO1TD
- PLG1C821MDO1
- PLG1C471MDO1
- PLG1C331MCO1
- PLFSWD
- PLF-6PC
- PLF6PC
- PLF6DZ2
- PLF-6D3
- PLF6D3
- PLF-6D1
- PLF6D1
- PLF60
- PLF3PC4
- PLF-3PC
- PLF3PC
- PLF3P4C
- PLF3DZ2
- PLF-3D3
- PLF3D3
- PLF30
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DdatasheetPDF页码索引
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