PLL1价格
参考价格：￥25.6860
型号：PLL1700E 品牌：TI 备注：这里有PLL1多少钱，2026年最近7天走势，今日出价，今日竞价，PLL1批发/采购报价，PLL1行情走势销售排行榜，PLL1报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
PLL1 | 30 mm Replacement Lenses for pilot lights PLLx (x=color) 文件：191.17 Kbytes Page：1 Pages | ALTECH |   | |
PLL1 | 包装：散装 描述：LENSPILOT LIGHT 30 MM WHITE 光电器件 配件 | ALTECH | | |
PLL1 | Cyclone III Device Handbook | INTEL 英特尔 | | |
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1705TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1706TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1706TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1706TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1706TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1706TC；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt | TI 德州仪器 | | ||
丝印代码：PLL1707；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
丝印代码：PLL1707；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
丝印代码：PLL1707；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
丝印代码：PLL1707；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
丝印代码：PLL1707I；3.3-V DUAL-PLL MULTICLOCK GENERATOR 1FEATURES • Qualified for Automotive Applications • 27-MHz Master Clock Input • Generated Audio System Clock – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 f S (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) | TI 德州仪器 | | ||
丝印代码：PLL1707I；3.3-V DUAL-PLL MULTICLOCK GENERATOR 1FEATURES • Qualified for Automotive Applications • 27-MHz Master Clock Input • Generated Audio System Clock – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 f S (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) | TI 德州仪器 | | ||
丝印代码：PLL1708；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
丝印代码：PLL1708；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
丝印代码：PLL1708；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
丝印代码：PLL1708；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
丝印代码：PLL1708；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
丝印代码：PLL1708；3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170 | TI 德州仪器 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | ALTERA 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | ALTERA 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | ALTERA 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | ALTERA 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | ALTERA 阿尔特 | | ||
PHASE LOCKED LOOP [Z-Communications, Inc.] FEATURES • Frequency Range: 988 - 1028 MHz • Step Size: 1000 KHz • PLL - Style Package APPLICATIONS • Basestations • Mobile Radios • Satellite Communications | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | |
PLL1产品属性
- 类型
描述
- Package size：
mm2
- Rating：
Catalog
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI/德州仪器 |
25+ |
SSOP20 |
32000 |
TI/德州仪器全新特价PLL1708DBQR即刻询购立享优惠#长期有货 |
|||
TI |
07+ |
SSOP20 |
1500 |
AI芯片,车规MCU原装现货/为新能源汽车电子行业采购保驾护航 |
|||
TI |
2430+ |
SSOP20 |
8540 |
只做原装正品假一赔十为客户做到零风险!! |
|||
TI |
2025+ |
SOP |
3925 |
全新原装、公司现货热卖 |
|||
TI |
25+ |
29 |
全新原装!优势库存热卖中! |
||||
TI |
25+ |
SSOP20 |
15258 |
原装现货库存QQ:373621633 3616872778 |
|||
TI德州仪器 |
22+ |
SSOP20 |
2000 |
原装正品现货假一罚十 |
|||
TIE |
26+ |
SSOP |
28000 |
原装正品价格优惠,长期优势供应 |
|||
TI |
23+ |
PSOP20 |
214 |
新到现货 全新原装 |
|||
BB |
2023+ |
SSOP |
53500 |
正品,原装现货 |
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- PLL1705DBQR
- PLL1705DBQ
- PLL1705
- PLL1700E
- PLL1700
- PLL-15-Y2-10
- PLL-14-Y2-10
- PLL1_C4
- PLL1_C3
- PLL1_C2
- PLL1_C1
- PLL1_C0
- PLI9080
- PLHS501
- PLH-3R
- PLH-2A
- PLH250P
- PLH250
- PLH-1R
- PLH16
- PLH120P
- PLH120
- PLH10AS7003R6P2B
- PLH10AS3711R0P2B
- PLH10AS2211R5P2B
- PLH10AS1612R1P2B
- PLH10AN7003R6P2B
- PLH10AN3711R0P2B
- PLH10AN2211R5P2B
- PLH10AN1612R1P2B
- PLG3535AA000
- PLG1C821MDO1TD
- PLG1C821MDO1
- PLG1C471MDO1
- PLG1C331MCO1
- PLFSWD
- PLF-6PC
- PLF6PC
- PLF6DZ2
- PLF-6D3
- PLF6D3
- PLF-6D1
- PLF6D1
- PLF60
- PLF3PC4
- PLF-3PC
- PLF3PC
- PLF3P4C
- PLF3DZ2
- PLF-3D3
- PLF3D3
- PLF30
PLL1数据表相关新闻
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2024-4-16PLED13Q12全新原装特价现货出售
PLED13Q12
2022-7-8PL-27A35ERQ
PL-27A35ERQ PLD-27A35WQ PLD-35A29WQ PS-521Q PLD-27N36WQ PS-562Q PS-593SCQ PT-1240PEQ PT-1520PQ PT-2045FWQ PT-2725PQ PT-2726FPQ KPEG122 KPEG1600 KMTG1603 KPEG522 F-B-M0403ESB LF KCG1202 KCG1206 KCVG084B16 KMI-1240 KMIG-1240 KMIG1240-A KMTG1003-F KMTG1102-A1 KMTG1203 KMTG1212
2021-4-27PLUS16L8-7N，PLUS16L8DN，PLUS16R4-7N，PLUS16R4DN，PLUS20L8-7N，
PLUS16L8-7N，PLUS16L8DN，PLUS16R4-7N，PLUS16R4DN，PLUS20L8-7N，
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2019-9-29PM2071LED单段线性驱动芯片
PM2071LED单段线性驱动芯片
2019-6-20
DdatasheetPDF页码索引
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