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PLL1价格
参考价格：￥25.6860
型号：PLL1700E 品牌：TI 备注：这里有PLL1多少钱，2025年最近7天走势，今日出价，今日竞价，PLL1批发/采购报价，PLL1行情走势销售排行榜，PLL1报价。| 型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
|---|---|---|---|---|
PLL1 | 30 mm Replacement Lenses for pilot lights PLLx (x=color) 文件：191.17 Kbytes Page：1 Pages | ALTECH |   | |
PLL1 | 包装：散装 描述：LENSPILOT LIGHT 30 MM WHITE 光电器件 配件 | ALTECH | | |
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
Cyclone III Device Handbook Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons | Altera 阿尔特 | | ||
PHASE LOCKED LOOP [Z-Communications, Inc.] FEATURES • Frequency Range: 988 - 1028 MHz • Step Size: 1000 KHz • PLL - Style Package APPLICATIONS • Basestations • Mobile Radios • Satellite Communications | ETCList of Unclassifed Manufacturers 未分类制造商 | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-03 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in an 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the inpu | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-05 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input o | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Programmable DDR Zero Delay Clock Driver DESCRIPTIONS The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purpose | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Low Skew Output Buffer DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the | PLL | | ||
Low Skew Output Buffer DESCRIPTIONS The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to t | PLL | | ||
Low Skew Output Buffer DESCRIPTIONS The PLL102-15 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to t | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
Low Skew Buffers FEATURES • Generate 18 copies of High-speed clock inputs. • Supports up to four SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50 duty cycle with low jitter. • Less than 5ns delay. • Skew between any outputs is less than 250 ps. • Tri-state pin f | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETC1List of Unclassifed Manufacturers etc未分类制造商未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETC1List of Unclassifed Manufacturers etc未分类制造商未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETC1List of Unclassifed Manufacturers etc未分类制造商未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS [PLL] DESCRIPTIONS The PLL103-02 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS or to support 2 unbuffered standard SDRAM DIMMS and 2 DDR DIMMS. The PLL103-02 | ETC1List of Unclassifed Manufacturers etc未分类制造商未分类制造商 | | ||
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS DESCRIPTIONS The PLL103-02 Rev.D is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 Rev.D can be used in conjunction with the PLL202-04 or similar clock syn | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS DESCRIPTIONS The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | | ||
1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out | PLL | |
PLL1产品属性
- 类型
描述
- 型号
PLL1
- 功能描述
开关配件 Lens, Pilot Light, 30 mm,White
- RoHS
否
- 制造商
C&K Components
- 类型
Cap
- 用于
Pushbutton Switches
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
BB/TI |
24+ |
NA/ |
3260 |
原厂直销,现货供应,账期支持! |
|||
TI(德州仪器) |
24+ |
SSOP20 |
7350 |
现货供应,当天可交货!免费送样,原厂技术支持!!! |
|||
TI |
2016+ |
QSOP20 |
3500 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
TI |
23+ |
SSOP-20 |
20000 |
全新原装假一赔十 |
|||
TI |
24+ |
SSOP20 |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
BURR-BROWN |
25+ |
NA |
880000 |
明嘉莱只做原装正品现货 |
|||
TI/德州仪器 |
22+ |
SSOP-20 |
100000 |
代理渠道/只做原装/可含税 |
|||
TI/德州仪器 |
25+ |
SSOP |
54648 |
百分百原装现货 实单必成 欢迎询价 |
|||
TI/德州仪器 |
25+ |
SSOP20 |
32000 |
TI/德州仪器全新特价PLL1708DBQR即刻询购立享优惠#长期有货 |
|||
TI |
23+ |
QSOP20 |
7566 |
原厂原装 |
PLL1规格书下载地址
PLL1参数引脚图相关
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- PLI9080
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- PLF60
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- PLF-3PC
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- PLF3P4C
- PLF3DZ2
- PLF-3D3
- PLF3D3
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DdatasheetPDF页码索引
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