位置：首页 > IC中文资料第5595页 > K4H511638D
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
K4H511638D | 512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 |   | |
K4H511638D | DDR SDRAM Product Guide Consumer Memory | Samsung 三星 | | |
K4H511638D | 512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | |
512Mb C-die DDR SDRAM Specification 文件：212.57 Kbytes Page：24 Pages | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif | Samsung 三星 | | ||
512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl | Samsung 三星 | | ||
512Mb B-die DDR SDRAM Specification 文件：392.89 Kbytes Page：24 Pages | Samsung 三星 | | ||
512Mb B-die DDR SDRAM Specification 文件：392.89 Kbytes Page：24 Pages | Samsung 三星 | | ||
512Mb B-die DDR SDRAM Specification 文件：392.89 Kbytes Page：24 Pages | Samsung 三星 | |
K4H511638D产品属性
- 类型
描述
- 型号
K4H511638D
- 制造商
SAMSUNG
- 制造商全称
Samsung semiconductor
- 功能描述
DDR SDRAM Product Guide
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
SAMSUNG/三星 |
24+ |
NA/ |
3538 |
原装现货,当天可交货,原型号开票 |
|||
SAMSUNG |
2016+ |
TSOP |
5000 |
全新原装现货,只售原装,假一赔十! |
|||
SAMSUNG |
22+ |
TSOP |
8000 |
原装正品支持实单 |
|||
SAMSUNG |
25+ |
ROHS |
12 |
全新原装!优势库存热卖中! |
|||
SAMSUNG |
TSOP |
140 |
正品原装--自家现货-实单可谈 |
||||
SAMSUNG |
25+ |
标准封装 |
18000 |
原厂直接发货进口原装 |
|||
SAMSUNG |
22+ |
TSOP |
2000 |
原装正品现货 |
|||
SAMSUNG |
新 |
2 |
全新原装 货期两周 |
||||
SAMSUNG |
24+ |
TSOP66 |
66500 |
郑重承诺只做原装进口现货 |
|||
SAMSUNG |
25+ |
480 |
公司现货库存 |
K4H511638D规格书下载地址
K4H511638D参数引脚图相关
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DdatasheetPDF页码索引
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