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K4H511638价格

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型号：K4H511638B-TCCC000 品牌：Samsung 备注：这里有K4H511638多少钱，2026年最近7天走势，今日出价，今日竞价，K4H511638批发/采购报价，K4H511638行情走势销售排行榜，K4H511638报价。

型号	功能描述	生产厂家企业	LOGO
K4H511638	512Mb C-die DDR SDRAM Specification 文件：212.57 Kbytes Page：24 Pages	Samsung 三星	Samsung
K4H511638A-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638A-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638A-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638A-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638A-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638A-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638B-TC/LA2	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-TC/LB0	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-TC/LB3	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-TC/LCC	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638B-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638B-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638B-TCSLASHLA2	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-TCSLASHLB0	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-TCSLASHLB3	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-TCSLASHLCC	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638B-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638B-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638B-UC/LA2	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-UC/LB0	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-UC/LB3	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-UC/LCC	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-UCSLASHLA2	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-UCSLASHLB0	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-UCSLASHLB3	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638B-UCSLASHLCC	512Mb B-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential cl	Samsung 三星	Samsung
K4H511638C-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638C-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638C-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638C-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638C-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638C-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638D	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D	DDR SDRAM Product Guide Consumer Memory	Samsung 三星	Samsung
K4H511638D	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-LA2	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-LB0	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-LB3	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-LCC	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638D-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638D-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638D-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638D-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638D-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H511638D-UC/LA2	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC/LA2	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC/LB0	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC/LB0	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC/LB3	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC/LB3	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC/LCC	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC/LCC	512Mb D-die DDR SDRAM Specification Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC0	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC2	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UC3	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung
K4H511638D-UCC	512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Key Features • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Dif	Samsung 三星	Samsung

K4H511638产品属性

类型
描述
型号
K4H511638
制造商
SAMSUNG
制造商全称
Samsung semiconductor
功能描述
512Mb C-die DDR SDRAM Specification

K4H511638供应商更多...

更新时间：2026-1-6 10:19:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市东来宝电子科技有限公司	K4H511638D-UCCC	SAMSUNG	24+	TSOP66	66500	郑重承诺只做原装进口现货	询价
深圳市羿芯诚电子有限公司	K4H511638D-UCCC	SAMSUNG	20+	TSSOPPB	2860	原厂原装正品价格优惠公司现货欢迎查询	询价
京海半导体(深圳)有限公司	K4H511638D-UCCC	SAMSUNG/三星	23+	TSOP	98900	原厂原装正品现货!!	询价
上海鑫科润电子科技有限公司	K4H511638J-LCCC	SAMSUNG	14+	TSOP66	9860	大量原装进口现货,一手货源,一站式服务,可开17%增	询价
深圳市富芯乐电子科技有限公司	K4H511638J-LCCC	SAMSUNG/三星	24+	TSOP-66	21356	全新原装现货特价销售,欢迎来电查询	询价
深圳市能创芯电子科技有限公司	K4H511638J-LCB3	Samsung	23+	TSOP	16800	进口原装现货	询价
深圳市科恒伟业电子有限公司	K4H511638J-LCCC	SAMSUNG	2430+	TSSOP	8540	只做原装正品假一赔十为客户做到零风险!!	询价
深圳市浩翊科技有限公司	K4H511638J-LCCC	SAMSUNG	13+	TSSOP	8000	原装正品	询价
海芯未来半导体电子（深圳）有限公司	K4H511638J-LCCC	SAMSUNG	24+	TSOP	6800		询价
深圳市华来深电子有限公司	K4H511638J-LCCC	SAMSUNG	23+	TSOP	1500	主打XILINX品牌价格绝对优势	询价

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K4H511638价格

K4H511638产品属性

K4H511638供应商更多...

K4H511638芯片相关品牌

K4H511638规格书下载地址

K4H511638参数引脚图相关

K4H511638数据表相关新闻

K4E6E304EB-EGCF

K4FBE3D4HB-KFC

K4F6E3S4HM-MGCJ

K4T1G164QG-BCE7 进口原装，主营军工级IC

K4S641632H-TC30，K4S641632H-UC6，K4SA160822DTC1H，K616V1002CT-12

K4T1G084QJ-BCE7

DdatasheetPDF页码索引