256/512/1K/2K/4K x 9 Asynchronous FIFO

文件：622.02 Kbytes Page：17 Pages

256/512/1K/2K/4K x 9 Asynchronous FIFO

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2163KV18, and CY7C2165KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port ha

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2163KV18, and CY7C2165KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port ha

18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the inpu

18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the inpu

同步 SRAM

封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 18MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

同步 SRAM

封装/外壳：165-LBGA 包装：托盘 描述：IC SRAM 18MBIT PARALLEL 165FBGA 集成电路（IC） 存储器

18-Mbit DDR II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

文件：771.86 Kbytes Page：24 Pages

18-Mbit DDR II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

文件：771.86 Kbytes Page：24 Pages